AD9864BCPZRL Analog Devices Inc, AD9864BCPZRL Datasheet
AD9864BCPZRL
Specifications of AD9864BCPZRL
Related parts for AD9864BCPZRL
AD9864BCPZRL Summary of contents
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FEATURES 10 MHz to 300 MHz input frequency 6.8 kHz to 270 kHz output signal bandwidth 7.5 dB SSB NF –7.0 dBm IIP3 AGC free range up to –34 dBm 12 dB continuous AGC range 16 dB front end attenuator ...
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AD9864 TABLE OF CONTENTS General Description ......................................................................... 3 AD9864 Specifications..................................................................... 4 Digital Specifications........................................................................ 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Pin Configuration and Functional Descriptions.......................... 8 Definition of Specifications/Test Methods ............................... 9 Typical Performance Characteristics ........................................... 10 Serial ...
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GENERAL DESCRIPTION The AD9864 is a general-purpose narrow-band IF subsystem that digitizes a low level 10 MHz to 300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 consists ...
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AD9864 AD9864 SPECIFICATIONS Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2 3.6 V, VDDQ = VDDP = 2 5 109.65 MHz 107.4 MHz, ...
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Parameter OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Digital Supply Voltage (VDDD, VDDC, VDDL) 1 Interface Supply Voltage (VDDH) Charge Pump Supply Voltage (VDDP, VDDQ) Total Current 2 Operation Mode Standby OPERATING TEMPERATURE RANGE 1 VDDH must be less than ...
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AD9864 DIGITAL SPECIFICATIONS Table 2. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2 3.6 V, VDDQ = VDDP = 2 5 109.65 MHz 107.4 MHz, ...
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ABSOLUTE MAXIMUM RATINGS Table 3. AD9864 Absolute Maximum Ratings Parameter VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDF, GNDA, GNDC, GNDD, GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, ...
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AD9864 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Figure 2. 48-Lead LFCSP, Backside Paddle Contact Is Connected to Ground Table 5. Pin Function Descriptions—48-Lead Lead Frame Chip Scale Package (LFCSP) Pin No. Mnemonic Description 1 MXOP Mixer Output, Positive 2 MXON Mixer ...
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DEFINITION OF SPECIFICATIONS/TEST METHODS Single Sideband Noise Figure (SSB NF) Noise figure (NF) is defined as the degradation in SNR per- formance (in dB input signal after it passes through a component or system. It can be ...
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AD9864 TYPICAL PERFORMANCE CHARACTERISTICS 9.5 9.0 +85°C 8.5 8.0 +25°C 7.5 7.0 –40°C 6.5 6.0 2.7 3.0 VDDx (V) Figure 3. SSB Noise Figure vs. Supply 98 97 +25° +85° 2.7 3.0 VDDx (V) Figure ...
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NF 8.0 7.8 IMD 7.6 7.4 7.2 7.0 –20 –15 –10 –5 LO DRIVE (dBm) Figure 9. Noise Figure and IMD vs. LO Drive (VDDx = 3 ADC DOES NOT GO INTO HARD ...
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AD9864 10.0 9.5 16-BIT DATA 9.0 8.5 8.0 7.5 10 100 CHANNEL BANDWIDTH (kHz) Figure 15. Noise Figure vs. BW (Minimum Attenuation 75kHz ( 50kHz (K = ...
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PIN –60 –70 –80 –90 –100 –110 –120 –130 –45 –42 –39 –36 –33 –30 IFIN (dBm) Figure 21. IMD vs. IFIN ( MSPS) CLK 13 16-BIT WITH DVGA 24-BIT 8 ...
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AD9864 16 15 AGC ATTN NOISE FIGURE –50 –45 –40 –35 –30 –25 INTERFERER LEVEL (dBm) Figure 27. Noise Figure vs. Interferer Level (16-Bit Data with DVGA 12.5 kHz, AGCR = ...
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SERIAL PERIPHERAL INTERFACE (SPI) The SPI is a bidirectional serial port used to load the configuration information into the registers listed below as well as to read back their contents. Table 6 provides a list of the registers ...
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AD9864 Bit Address (Hex) Breakdown Width 0x13 (7:0) 8 0x14 (6) 1 (5) 1 (4:2) 3 (1:0) 2 0x15 (5:0) 6 0x16 (7:0) 8 SSI CONTROL 0x18 (7:0) 8 0x19 (7:0) 8 0x1A (3:0) 4 ADC TUNING 0x1C (1) 1 ...
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THEORY OF OPERATION SERIAL PORT INTERFACE (SPI) The serial port of the AD9864 has 3-wire or 4-wire SPI capabil- ity, allowing read/write access to all registers that configure the device’s internal parameters. The default 3-wire serial commu- nication port consists ...
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AD9864 DON'T T DOUTB CARE SYNCHRONOUS SERIAL INTERFACE (SSI) The AD9864 provides a high degree of programmability of its SSI output data format, control signals, and timing parameters to accommodate various digital interfaces ...
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Table 8. SSI Control Registers Name Width Default SSICRA (ADDR = 0x18) AAGC 1 0 EAGC 1 0 EFS 1 0 SFST 1 1 SFSI 1 0 SLFS 1 0 SCKT 1 1 SCKI 1 0 SSICRB (ADDR = 0x19) ...
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AD9864 CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, ...
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Table 9. Number of Bits per Frame for Different SSICR Settings DW EAGC EFS 0 (16 Bit (24 Bit ...
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AD9864 14 13 24-BIT I/O DATA 16-BIT I/O DATA SSI OUTPUT DRIVE STRENGTH SETTING Figure 35. NF vs. SSI Output Drive Strength (VDDx = 3 MSPS, ...
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POWER CONTROL To allow power consumption to be minimized, the AD9864 possesses numerous SPI programmable power-down and bias control bits. The AD9864 powers up with all of its functional blocks placed into a standby state, i.e., STBY register default is ...
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AD9864 The stability, phase noise, spur performance, and transient response of the AD9864’s LO (and CLK) synthesizers are determined by the external loop filter, the VCO, the N-divide factor, and the reference frequency, f REF theory and practical implementation of ...
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The 14-bit reference counter and 13-bit N-divider counter can be programmed via registers CKR and CKN. The clock frequency related to the reference frequency by the equation CLK ( ) = × f CKN / CKR f ...
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AD9864 Table 13. SPI Registers Associated with CLK Synthesizer Address Bit (Hex) Breakdown Width 0x00 (7:0) 8 0x01 (3:2) 2 0x10 (5:0) 6 0x11 (7:0) 8 0x12 (4:0) 5 0x13 (7:0) 8 0x14 (6) 1 (5) 1 (4:2) 3 (1:0) ...
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L C CLK For example MHz and µH, a capacitance of CLK 250 pF is needed. However, ...
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AD9864 0 –10 –20 –30 NOTCH AT ALL ALIAS FREQUENCIES –40 –50 –60 –70 –80 0 0.5 1.0 NORMALIZED FREQUENCY (RELATIVE TO Figure 48. Signal Transfer Function of the Band-Pass Σ-∆ Modulator from CLK Figure 49 ...
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BW = 75kHz 30kHz 10kHz 8 –15 –10 –5 ...
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AD9864 3 2 PASS-BAND GAIN FREQUENCY = 1.2dB 1 0 –1 –2 –3 0 0.125 NORMALIZED FREQUENCY (RELATIVE TO Figure 54. Pass-Band Frequency Response of the Decimator for PASS-BAND GAIN VARIATION = 0.9dB 1 0 ...
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ADC - DEC1 C1 ÷12 FS VGA DAC GCP C DAC VARIABLE GAIN CONTROL The variable gain control is enabled by setting the AGCR field of Register 0x06 this mode, the gain of the VGA ...
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AD9864 0 –3 –6 –9 –12 –15 –18 0 0.01 0.02 0.03 NORMALIZED FREQUENCY OFFSET (( Figure 60. Normalized RSSI Error vs. Normalized IF Frequency Offset AUTOMATIC GAIN CONTROL (AGC) The gain of the VGA (and DVGA) is automatically adjusted ...
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The decay time may be computed from ( ) = × AGCD DECAY ATTACK Figure 61 shows the AGC response pulse-modulated ...
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AD9864 option, the use of 24-bit data is preferable to using the DVGA. Table 17 indicates which AGCA values are reasonable for various decimation factors. The white cells indicate that the (decimation factor/AGCA) combination works well; the light gray cells ...
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NF will increase because of the quantization noise present in the 16-bit data after truncation 50kHz 150kHz 11 SNR = 82.9dBFS 10kHz 9 ...
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AD9864 which low level spurs can degrade the AD9864’s sensitivity performance. Despite the many spurs, sweet spots in the LO frequency are generally wide enough to accommodate the maximum signal –50 –60 –70 –80 – Figure 66. Total ...
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LO FREQUENCY (MHz) Figure 68. Expanded View from 70 MHz to 71 MHz 4.5MHz CLK –20 DESIRED RESPONSES –40 –60 –80 –100 –120 ...
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AD9864 The LO, CLK, and IFIN signals are coupled to their respective inputs using 10 nF capacitors. The output of the mixer is cou- pled to the input of the ADC using 100 pF. An external 100 kΩ resistor from ...
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Figure 71 shows a typical dual conversion superheterodyne receiver using the AD9864 tuner is used to select and downconvert the target signal to a suitable first IF for the AD9864. A preselect filter may precede the tuner to ...
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AD9864 VDDC LOOP FILTER R BIAS C 0.1µF OSC OSC VAR IOUTC FREF 19 CLKP 20 CLKN 47 IFIN FS DOUTA CLKOUT 43 LOP PE 42 LON PD AD9864 ...
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DUPLEXER PRESELECT LNA MIXER GAIN = –2dB GAIN = 22dB GAIN = –3dB NF = 2dB NF = 1dB NF = 3dB Figure 73. Example of Split Path Rx Architecture to Increase Receiver Dynamic Range Capabilities Hung Mixer Mode The ...
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AD9864 105 100 MAX ATTEN WITH 24-BIT I/Q DATA 95 MAX ATTEN WITH 16-BIT I/Q DATA 90 85 MIN ATTEN WITH 24-BIT I/Q DATA 100 BW (kHz) Figure 74. Hung Mixer SNR vs. BW ...
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... ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE AD9864 Products Temperature Package AD9864BCPZ* –40°C to +85°C AD9864BCPZRL* –40°C to +85°C AD9864-EB *This is a lead free product. 7.00 BSC SQ 0.60 MAX 37 ...
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AD9864 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. C04319-0-8/03(0) Rev Page ...