AD9864BCPZRL Analog Devices Inc, AD9864BCPZRL Datasheet - Page 23

• Manufacturer Part Number: AD9864BCPZRL
• Description: IC,RF/Baseband Circuit,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9864BCPZRL

• Rf Type: UHF, Cellular, GSM, EDGE, TETRA
• Frequency: 10MHz ~ 300MHz
• Features: General Purpose IF Subsystem
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER CONTROL
To allow power consumption to be minimized, the AD9864
possesses numerous SPI programmable power-down and bias
control bits. The AD9864 powers up with all of its functional
blocks placed into a standby state, i.e., STBY register default is
0xFF. Each major block may then be powered up by writing a 0
to the appropriate bit of the STBY register. This scheme pro-
vides the greatest flexibility for configuring the IC to a specific
application as well as for tailoring the IC’s power-down and
wake-up characteristics. Table 11 summarizes the function of
each of the STBY bits. Note that when all the blocks are in
standby, the master reference circuit is also put into standby,
and thus the current is reduced further by 0.4 mA.
Table 11. Standby Control Bits
STBY Bit
7: REF
6: LO
5: CKO
4: CK
3: GC
2: LNAMX
1: Unused
0: ADC
NOTES
1
2
LO SYNTHESIZER
The LO synthesizer shown in Figure 38 is a fully programmable
phase-locked loop (PLL) capable of 6.25 kHz resolution at
input frequencies up to 300 MHz and reference clocks of up to
25 MHz. It consists of a low noise digital phase-frequency
detector (PFD), a variable output current charge pump (CP), a
14-bit reference divider, programmable A and B counters, and
a dual-modulus 8/9 prescaler.
The A (3-bit) and B (13-bit) counters, in conjunction with the
dual 8/9 modulus prescaler, implement an N divider with N = 8
× B + A. In addition, the 14-bit reference counter (R Counter)
allows selectable input reference frequencies, f
When all blocks are in standby, the master reference circuit is also put into
Wake-up time is dependent on programming and/or external components.
standby, and thus the current is further reduced by 0.4 mA.
Effect
Voltage reference OFF;
all biasing shut down.
LO synthesizer OFF,
IOUTL three-state.
Clock oscillator OFF.
Clock synthesizer OFF,
IOUTC three-state. Clock
buffer OFF if ADC is OFF.
Gain control DAC OFF.
GCP and GCN three-
state.
LNA and Mizer OFF.
CXVM, CXVL, and CXIF
three-state.
ADC OFF; Clock buffer
OFF if CLK synthesizer
OFF; VCM three-state;
clock to the digital filter
halted; digital outputs
static.
Current
Reduction
(mA)
0.6
1.2
1.1
1.3
0.2
8.2
9.2
REF
1
, at the PFD
Wake-Up
Time (ms)
<0.1 (C
= 4.7 nF)
Note 2
Note 2
Note 2
Depends
on C
<2.2
<0.1
Rev. 0 | Page 23 of 44
GC
REF
input. A complete PLL can be implemented if the synthesizer is used
with an external loop filter and voltage controlled oscillator (VCO).
The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output
current is programmable via the LOI register from 0.625 mA to
5.0 mA using the equation
An on-chip fast acquire function (enabled by the LOF bit)
automatically increases the output current for faster settling
during channel changes. The synthesizer may also be disabled
using the LO standby bit located in the STBY register.
The LO (and CLK) synthesizer works in the following manner.
The externally supplied reference frequency, f
and divided by the value held in the R counter. The internal f
is then compared to a divided version of the VCO frequency,
f
pulses whose widths vary, depending upon the difference in
phase and frequency of the detector’s input signals. The
UP/DOWN pulses control the charge pump, making current
available to charge the external low-pass loop filter when there
is a discrepancy between the inputs of the PFD. The output of
the low-pass filter feeds an external VCO whose output fre-
quency, f
matches that of f
The synthesized frequency is related to the reference frequency
and the LO register contents as follows:
Note that the minimum allowable value in the LOB register is 3
and its value must always be greater than that loaded into LOA.
An example may help illustrate how the values of LOA, LOB, and
LOR can be selected. Consider an application employing a 13
MHz crystal oscillator, i.e., f
that f
with f
130 such that f
can be realized by selecting LOB = 178 and LOA = 6.
f
LO
REF
. The phase/frequency detector provides UP and DOWN
BUFFER
REF
IPUMP
f
IF
REF
LO
= 140.75 MHz and f
= 100 kHz and f
LO
=
, is driven such that its divided down version, f
(
8
=
×
REF
(
LOB
LOI
REF
LOR
LOA, LOB
= 100 kHz. The N-divider factor is 1430, which
÷R
, thus closing the feedback loop.
COUNTERS
+
+
1 ×
f
LOA
Figure 38. LO Synthesizer
REF
A. B
)
LO
. 0
)
= 143 MHz, i.e., high side injection
FREQUENCY
625
DETECTOR
f
/
CLK
REF
LO
PHASE/
LOR
= 18 MSPS. LOR is selected to be
= 13 MHz, with the requirement
mA
×
÷8/9
f
REF
ACQUIRE
BUFFER
CHARGE
FAST
PUMP
REF
LO
, is buffered
TO EXTERNAL
AD9864
FILTER
LOOP
f
FROM
VCO
LO
LO
,
REF
(2)
(3)