AD9753ASTZ Analog Devices Inc, AD9753ASTZ Datasheet - Page 2

• Manufacturer Part Number: AD9753ASTZ
• Description: 12-Bit, 300 MSPS TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9753ASTZ

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Number Of Channels: 1
• Resolution: 12b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Segment
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package: 48LQFP
• Conversion Rate: 300 MSPS
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Full Scale Error: ±2 %FSR
• Integral Nonlinearity Error: ±1.5 LSB
• Maximum Settling Time: 0.011(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9753-EB - BOARD EVAL FOR AD9753
• Lead Free Status / Rohs Status: Compliant

AD9753–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
ANALOG OUTPUT
REFERENCE OUTPUT
REFERENCE INPUT
TEMPERATURE COEFFICIENTS
POWER SUPPLY
OPERATING RANGE
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
Measured at I
Nominal full-scale current, I
An external buffer amplifier is recommended to drive any external load.
100 MSPS f
300 MSPS f
± 5% power supply variation.
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
Output Compliance Range
Output Resistance
Output Capacitance
Reference Voltage
Reference Output Current
Input Compliance Range
Reference Input Resistance
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
Supply Voltages
Analog Supply Current (I
Digital Supply Current (I
PLL Supply Current (I
Clock Supply Current (I
Power Dissipation
Power Dissipation
Power Supply Rejection Ratio
Power Supply Rejection Ratio
AVDD
DVDD
PLLVDD
CLKVDD
DAC
DAC
OUTA
.
with PLL on, f
, driving a virtual ground.
1
4
5
(3 V, I
(3 V, I
OUTFS
PLLVDD
OUT
CLKVDD
DVDD
, is 32× the I
AVDD
OUTFS
OUTFS
3
2
= 1 MHz, all supplies = 3.0 V.
(T
otherwise noted.)
)
6
6
)
)
4
—AVDD
—DVDD
4
4
MIN
)
4
= 20 mA)
= 20 mA)
to T
REF
MAX
current.
, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, I
–2–
Min
12
–1.5
–1
–0.025
–2
–2
2.0
–1.0
1.14
0.1
3.0
3.0
3.0
3.0
–1
–0.04
–40
Typ
± 0.5
± 0.4
± 0.01
± 0.5
± 0.25
100
5
1.20
100
1
0
± 50
± 100
± 50
3.3
3.3
3.3
3.3
33
3.5
4.5
10.0
155
216
Max
+1.5
+1
+0.025
+2
+2
20.0
1.26
1.25
3.6
3.6
3.6
3.6
36
4.5
5.1
11.5
165
+1
+0.04
+1.25
+85
OUTFS
= 20 mA, unless
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
MΩ
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
REV.B