AD9753-EB Analog Devices Inc, AD9753-EB Datasheet
AD9753-EB
Specifications of AD9753-EB
Related parts for AD9753-EB
AD9753-EB Summary of contents
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... CMOS process. It operates from a single supply of 3 3.6 V and consumes 155 mW of power. PRODUCT HIGHLIGHTS 1. The AD9753 is a member of a pin compatible family of high speed TxDAC+s providing 10-, 12-, and 14-bit resolution. 2. Ultrahigh Speed 300 MSPS Conversion Rate. 3. Dual 12-Bit Latched, Multiplexed Input Ports. The AD9753 features a flexible digital interface allowing high speed data conversion through either a single or dual port input ...
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... AD9753–SPECIFICATIONS ( MIN DC SPECIFICATIONS otherwise noted.) Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance ...
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... Specifications subject to change without notice. REV AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3 MIN MAX Differential Transformer-Coupled Output Doubly Terminated, unless otherwise noted.) Min ) 300 82.5 –3– AD9753 = 20 mA, OUTFS Typ Max Unit MSPS pV-s 2 pA/√Hz 30 pA/√Hz ...
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... AD9753 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Logic 0 Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time ( 25° Input Hold Time ( 25° Latch Pulsewidth ( 25°C LPW A Input Setup Time (t , PLLVDD = 0 V Input Hold Time (t , PLLVDD = 0 V CLK to PLLLOCK Delay (t , PLLVDD = 0 V), T ...
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... ACOM, DCOM, CLKCOM, PLLCOM AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM ACOM ACOM DCOM CLKCOM CLKCOM PLLCOM Model AD9753AST AD9753ASTRL –40°C to +85°C 48-Lead LQFP ST-48 AD9753- DATA Y DATA X THERMAL CHARACTERISTIC Thermal Resistance 48-Lead LQFP = 91°C/W JA –5– AD9753 ...
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... CLKCOM 46 LPF 47 PLLVDD 48 CLKVDD PIN CONFIGURATION RESET 1 PIN 1 CLK+ 2 IDENTIFIER CLK– 3 DCOM 4 DVDD 5 AD9753 PLLLOCK 6 TOP VIEW 7 (Not to Scale) P1B10 8 P1B9 9 P1B8 10 P1B7 11 P1B6 PIN FUNCTION DESCRIPTIONS Description Internal Clock Divider Reset Differential Clock Input Differential Clock Input Digital Common ...
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... PULSE GENERATOR (FOR DATA RETIMING) PLL DISABLED PLL ENABLED Figure 2. Basic AC Characterization Test Setup –7– MINI TO ROHDE & CIRCUITS SCHWARZ I T1-1T FSEA30 OUTA SPECTRUM I OUTB 50 ANALYZER PLLVDD CLKVDD 50 RESET PLL LPF CLKCOM DIV0 DIV1 PLLLOCK 1k 3.0V TO 3.6V 1k HP8644 SIGNAL GENERATOR AD9753 ...
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... AD9753–Typical Performance Characteristics 90 0dBmFS 80 70 –6dBmFS 60 –12dBmFS (MHz) OUT TPC 1. Single-Tone SFDR vs OUT MSPS, Single-Port Mode DAC 90 80 200MSPS 70 60 65MSPS 300MSPS 100 120 140 f (MHz) OUT TPC 4. SFDR vs dBFS OUT 90 11.82MHz @ 130MSPS 80 18.18MHz @ 200MSPS 70 60 27.27MHz @ 300MSPS 50 40 –16 – ...
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... CODE TPC 17. Typical DNL –9– AD9753 90 26MHz/27MHz @ 130MSPS 80 70 40MHz/41MHz 60 @ 200MSPS 50 60MHz/61MHz @ 300MSPS 40 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 ...
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... AD9753 DCOM ACOM FUNCTIONAL DESCRIPTION Figure 3 shows a simplified block diagram of the AD9753. The AD9753 consists of a PMOS current source array capable of providing full-scale current, I array is divided into 31 equal sources that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... Figure 7 defines the input and output timing for the AD9753 with the PLL active. CLK in Figure 7 represents the clock that is generated external to the AD9753. The input data at both Ports 1 and 2 is latched on the same CLK rising edge. CLK may be applied as a single-ended signal by tying CLK– to midsupply and applying CLK to CLK differential signal applied to CLK+ and CLK– ...
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... The speed and timing of the data present at input Ports 1 and 2 are now dependent on whether or not the AD9753 is interleaving the digital input data or only responding to data on a single port. Figure functional block diagram of the AD9753 clock control circuitry with the PLL disabled ...
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... CLK rising edge will toggle PLLLOCK. REV. B NONINTERLEAVED MODE WITH PLL DISABLED If the data at only one port is required, the AD9753 interface can operate as a simple double buffered latch with no interleaving. On the rising edge of the 1× clock, input latch updated with the present input data (depending on the state of DIV0/ DIV1) ...
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... I can be OUTA OUTB shown in Figures 7 and 11. The AD9753 is designed to support an input data rate as high as 150 MSPS, giving a DAC output update rate of 300 MSPS. The setup-and-hold times can also be varied within the clock cycle as long as the specified mini- mum times are met. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock ...
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... Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. Inserting a low value resis- tor network (i.e., 20 Ω to 100 Ω) between the AD9753 digital inputs and driver outputs may be helpful in reducing any over- shooting and ringing at the digital inputs that contribute to data feedthrough ...
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... I symmetrically around ACOM and should be maintained with DAC the specified output compliance range of the AD9753. A differ- ential resistor, R output of the transformer is connected to the load, R –16– is set to a nominal 20 mA. For applications requir- and/ connected to an appropriately OUTB , referred to ACOM ...
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... In this case, AVDD, which is the positive analog supply for both the AD9753 and the op amp, is also used to level-shift the differen- tial output of the AD9753 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... Figure 27. 16 QAM Constellation, Gray Coded (Two 4-Level PAM Signals with Orthogonal Carriers) Typically, the I and Q data channels are quadrature-modulated in the digital domain. The high data rate of the AD9753 allows extremely wideband (>10 MHz) quadrature carriers to be syn- thesized. Figure 28 shows an example MSymbol/S QAM ...
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... In Figure 28, the adjacent channel power ratio (ACPR) at the output of the AD9753 is measured dB. The limitation on making a measurement of this type is often not the DAC but the noise inherent in creating the digital data record using computer tools ...
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... QAM with the BER of 1e-6, using the E/NO ratio is much greater than the worst-case SFDR, the noise will dominate the BER calculation. The AD9753 has a worst-case in-band SFDR the upper end of its frequency spectrum (see TPCs 4 and 7). When used to synthesize high level QAM signals as described above, noise, as opposed to distortion, will dominate its performance in these applications ...
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... EVALUATION BOARD The AD9753- evaluation board for the AD9753 TxDAC. Careful attention to layout and circuit design, combined with prototyping area, allows the user to easily and effectively evalu- ate the AD9753 in different modes of operation. Referring to Figures 34 and 35, the AD9753’s performance can be evaluated differentially or single-ended either using a trans- former, or directly coupling the output ...
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... P1B10 VALUE P1B09 1 P1B08 P1B07 1B05 13 P1B06 3 14 1B04 P1B05 15 4 1B03 P1B04 16 5 P1B03 1B02 17 P1B02 6 18 1B01 P1B01 AD9751/AD9753/AD9755 19 7 P1B00 LSB 1B00 1O15 DVDD PLANE 1O16 9 22 JP10 23 MSB 10 P2B13 24 1O17 P2B12 P2B11 RN9 P2B10 VALUE P2B09 1 P2B08 ...
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... TP13 RED DVDD PLANE TP14 DVDD PLANE BLK TP15 RED AVDD PLANE TP16 BLK TP17 RED CLKVDD JP7 TP11 PLLVDD PLANE B BLK 3 Figure 35. Evaluation Board Clock Circuitry –23– AD9753 CLK JP4 PGND BYPASS CAPS PINS 5, 6 PINS PINS 41, 44 ...
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... AD9753 Figure 36. Evaluation Board, Assembly—Top Figure 37. Evaluation Board, Assembly—Bottom –24– REV. B ...
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... Figure 39. Evaluation Board, Layer 2, Ground Plane REV. B Figure 38. Evaluation Board, Top Layer –25– AD9753 ...
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... AD9753 Figure 40. Evaluation Board, Layer 3, Power Plane Figure 41. Evaluation Board, Bottom Layer –26– REV. B ...
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... Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 SEATING PLANE 10 6 0.20 2 0.09 VIEW A 7 3.5 0 SEATING 0.08 MAX PLANE COPLANARITY VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC –27– 9.00 BSC PIN 1 7.00 TOP VIEW BSC SQ (PINS DOWN 0.27 0.50 0.22 BSC 0.17 AD9753 ...
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... AD9753 Revision History Location 9/03—Data Sheet changed from REV REV. B. Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to Figure Changes to Figure Changes to FUNCTIONAL DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure Changes to Figure Changes to Figure DIGITAL INPUTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Figure 1/03— ...