AD9753ASTZ Analog Devices Inc, AD9753ASTZ Datasheet - Page 18

• Manufacturer Part Number: AD9753ASTZ
• Description: 12-Bit, 300 MSPS TxDAC+ DAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9753ASTZ

• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Number Of Channels: 1
• Resolution: 12b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Segment
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package: 48LQFP
• Conversion Rate: 300 MSPS
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Full Scale Error: ±2 %FSR
• Integral Nonlinearity Error: ±1.5 LSB
• Maximum Settling Time: 0.011(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9753-EB - BOARD EVAL FOR AD9753
• Lead Free Status / Rohs Status: Compliant

AD9753
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR versus the frequency of the AD9753
AVDD supply over this frequency range is shown in Figure 25.
Note that the units in Figure 25 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on AVDD will thus be added in a
nonlinear manner to the desired I
different size of these switches, PSRR is very code-dependent.
This can produce a mixing effect that can modulate low fre-
quency power supply noise to higher frequencies. Worst-case
PSRR for either one of the differential DAC outputs will occur
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 25 represents a worst-
case condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC out-
put being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and, for
simplicity sake (i.e., ignore harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise superimposed on the DAC’s
full-scale current, I
using Figure 25 at 250 kHz. To calculate the PSRR for a given
R
V/V, adjust the curve in Figure 25 by the scaling factor 20 × Log
(R
by 34 dB, i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 25, becomes 51 dB V
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9753 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a system.
In general, AVDD, the analog supply, should be decoupled to
ACOM, the analog common, as close to the chip as physically
LOAD
LOAD
, such that the units of PSRR are converted from A/V to
). For instance, if R
85
80
75
70
65
60
55
50
45
40
Figure 25. Power Supply Rejection Ratio
0
2
OUTFS
, one must determine the PSRR in dB
4
FREQUENCY (MHz)
OUTFS
LOAD
OUT
. AC noise on the dc supplies is
/V
is 50 Ω, the PSRR is reduced
6
IN
OUT
.
. Due to the relative
8
10
12
–18–
possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for
both the analog and digital supplies, a clean analog supply may
be generated using the circuit shown in Figure 26. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
APPLICATIONS
QAM/PSK Synthesis
Quadrature modulation (QAM or PSK) consists of two base-
band PAM (Pulse Amplitude Modulated) data channels. Both
channels are modulated by a common frequency carrier. How-
ever, the carriers for each channel are phase-shifted 90° from
each other. This orthogonality allows twice the spectral efficiency
(data for a given bandwidth) of digital data transmitted via AM.
Receivers can be designed to selectively choose the “in phase” and
“quadrature” carriers, and then recombine the data. The recombi-
nation of the QAM data can be mapped as points representing
digital words in a two dimensional constellation as shown in
Figure 27. Each point, or symbol, represents the transmission of
multiple bits in one symbol period.
Typically, the I and Q data channels are quadrature-modulated
in the digital domain. The high data rate of the AD9753 allows
extremely wideband (>10 MHz) quadrature carriers to be syn-
thesized. Figure 28 shows an example of a 25 MSymbol/S QAM
signal, oversampled by 8 at a data rate of 200 MSPS, modu-
lated onto a 25 MHz carrier and reconstructed using the
AD9753. The power in the reconstructed signal is measured
to be –11.92 dBm. In the first adjacent band, the power is
–76.86 dBm, while in the second adjacent band, the power is
–80.96 dBm.
Figure 26. Differential LC Filter for a Single 3.3 V Application
Figure 27. 16 QAM Constellation, Gray Coded (Two
4-Level PAM Signals with Orthogonal Carriers)
TTL/CMOS
CIRCUITS
POWER SUPPLY
LOGIC
3.3V
0100
0110
1110
1100
FERRITE
BEADS
0101
0111
1111
1101
ELECT.
100 F
0001
0011
1011
1001
TANT.
10 F
0000
0010
1010
1000
0.1 F
CER.
REV. B
AVDD
ACOM