AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet - Page 27

• Manufacturer Part Number: AD7631BCPZ
• Description: IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7631BCPZ

• Number Of Bits: 18
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 44 shows the detailed timing diagrams for this method.
After a conversion is completed, indicated by BUSY returning low,
the conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 18 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
In addition, in the read after convert mode, the AD7631 provides a
daisy-chain feature for cascading multiple converters together
using the serial data input pin, SDIN. This feature is useful for
reducing component count and wiring connections when desired,
for instance, in isolated multiconverter applications. See Figure 44
for the timing details.
An example of the concatenation of two devices is shown
in Figure 43.
Simultaneous sampling is possible by using a common CNVST
signal. Note that the SDIN input is latched on the opposite edge
of SDCLK used to shift out the data on SDOUT (SDCLK
falling edge when INVSCLK = low). Therefore, the MSB of
the upstream converter follows the LSB of the downstream
converter on the next SDCLK cycle. In this mode, the 40 MHz
SDCLK rate cannot be used because the SDIN to SDCLK setup
time, t
to SDOUT delay, t
simultaneously sampled). For proper operation, the SDCLK
edge for latching SDIN (or ½ period of SDCLK) needs to be
Or the maximum SDCLK frequency needs to be
If not using the daisy-chain feature, the SDIN input should
always be tied either high or low.
t
f
1
33
SDCLK
2 /
, is less than the minimum time specified. (SDCLK
SDCLK
=
=
( 2
t
t
32
32
32
+
1
, is the same for all converters when
+
t
t
33
33
)
Rev. A | Page 27 of 32
External Clock Data Read During Previous Conversion
Figure 45 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 18 clock pulses and is valid on both the falling
and rising edges of the clock. The 18 bits have to be read before
the current conversion is completed; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR
conversion phase.
The daisy-chain feature should not be used in this mode because
digital activity occurs during the second half of the SAR
conversion phase likely resulting in performance degradation.
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
This method allows the full throughput and the use of a slower
SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize
potential incorrect bit decisions. The use of a slower SDCLK,
such as 13 MHz, can be used.
SDCLK IN
CNVST IN
CS IN
Figure 43. Two AD7631 Devices in a Daisy-Chain Configuration
RDC/SDIN SDOUT
(UPSTREAM)
AD7631
BUSY
#2
CNVST
SDCLK
CS
RDC/SDIN
(DOWNSTREAM)
AD7631
BUSY
#1
SDOUT
CNVST
SDCLK
CS
AD7631
BUSY
OUT
DATA
OUT