AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet - Page 29

• Manufacturer Part Number: AD7631BCPZ
• Description: IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7631BCPZ

• Number Of Bits: 18
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HARDWARE CONFIGURATION
The AD7631 can be configured at any time with the dedicated
hardware pins BIPOLAR, TEN, D0/OB/ 2C , and PD for parallel
mode (MODE[1:0] = 0, 1, or 2) or serial hardware mode
(MODE[1:0] = 3, HW/ SW = high). Programming the AD7631
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle, as indicated in
Figure 46
inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[17:14] used for software
configuration are: HW/ SW , SCIN, SCCLK, and SCCS . The
AD7631 is programmed using the dedicated write-only
serial configurable port (SCP) for conversion mode, input range
selection, output coding, and power-down using the serial
configuration register. See
configuration register. The SCP can only be used in serial software
mode selected with MODE[1:0] = 3 and HW/
the port is multiplexed on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS ,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See
configuration register MSB first. The configuration register is
an internal shift register that begins with Bit 8, the START bit.
The 9
settings to be used. As indicated in the timing diagram, at least one
acquisition time is required from the 9
reserved bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7631 is not busy
converting, as detailed in Figure 47. In this mode, the full
670 kSPS is not attainable because the time required for SCP
access is (t
Figure 47
th
SCCLK edge updates the register and allows the new
. See
31
+ 9 × 1/SCCLK + t
for timing details. SCIN is clocked into the
Table 6
for pin descriptions. Note that these
D0/OB/2C,
BIPOLAR,
CNVST
Table 11
BUSY
TEN
PD
8
) minimum. If the full
for details of each bit in the
th
SCCLK edge. Bits [1:0] are
SW = low because
t
8
Figure 46. Hardware Configuration Timing
HW/SW = 1
Rev. A | Page 29 of 32
PD = 0
throughput is required, the SCP can be written to during
conversion; however, it is not recommended to write to the SCP
during the last 600 ns of conversion (BUSY = high) or performance
degradation can result. In addition, the SCP can be accessed in
both serial master and serial slave read during and read after
convert modes.
Note that at power-up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), therefore placing the configuration to 0 V to 5 V input,
normal mode, and twos complemented output.
Table 11. Configuration Register Description
Bit
8
7
6
5
4
3
2
1
0
Mnemonic
START
BIPOLAR
TEN
PD
RSV
RSV
OB/2C
RSV
RSV
Description
START bit. With the SCP enabled (SCCS = low),
when START is high, the first rising edge of
SCCLK (INVSCLK = low) begins to load the
register with the new configuration.
Input Range Select. Used in conjunction with
Bit 6, TEN, per the following.
Input Range (V)
0 to 5
0 to 10
±5
±10
Input Range Select. See Bit 7, BIPOLAR.
Power Down.
PD = low, normal operation.
PD = high, power down the ADC. The SCP is
accessible while in power down. To power up
the ADC, write PD = low on the next
configuration setting.
Reserved.
Reserved.
Output coding.
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
Reserved.
Reserved.
t
8
BIPOLAR
Low
Low
High
High
AD7631
TEN
Low
High
Low
High