AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet - Page 26

• Manufacturer Part Number: AD7631BCPZ
• Description: IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7631BCPZ

• Number Of Bits: 18
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7631
SLAVE SERIAL INTERFACE
The pins multiplexed on D[13:6] used for slave serial
interface are: EXT/ INT , INVSCLK, SDIN, SDOUT, SDCLK,
and RDERROR.
External Clock (MODE[1:0] = 3, EXT/ INT = High)
Setting the EXT/ INT = high allows the AD7631 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The external
serial clock is gated by CS . When CS and RD are both low, the
data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally
low when inactive. For detailed timing diagrams, see
and
Figure 45
.
SDOUT
CS, RD
CNVST
SDCLK
BUSY
SYNC
SDOUT
CS, RD
CNVST
SDCLK
BUSY
SYNC
t
16
t
3
Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
t
t
t
t
t
14
15
14
15
16
t
t
29
X
17
t
t
22
18
Figure 42. Master Serial Data Timing for Reading (Read After Convert)
MODE[1:0] = 3
t
1
t
D17
3
t
1
20
X
t
t
22
19
MODE[1:0] = 3
t
21
t
20
Figure 44
D16
t
2
23
EXT/INT = 0
D17
1
t
t
18
19
Rev. A | Page 26 of 32
EXT/INT = 0
t
D16
3
21
t
2
23
RDC/SDIN = 1
t
28
3
RDC/SDIN = 0
While the AD7631 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is
particularly important during the last 550 ns of the conversion
phase because the AD7631 provides error correction circuitry
that can correct for an improper bit decision made during
the first part of the conversion phase. For this reason, it is
recommended that any external clock provided is a
discontinuous clock that transitions only when BUSY is low,
or, more importantly, that it does not transition during the
last 450 ns of BUSY high.
INVSCLK = INVSYNC = 0
D2
16
INVSCLK = INVSYNC = 0
16
D2
17
D1
17
D1
18
t
24
18
t
D0
30
t
24
D0
t
t
t
25
26
27
t
t
25
26
t
27