AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet
AD7631BCPZ
Specifications of AD7631BCPZ
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AD7631BCPZ Summary of contents
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FEATURES Multiple pins/software-programmable input ranges +5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p), ±10 V (40 V p-p) Pins or serial SPI-compatible input ranges/mode selection Throughput: 250 kSPS INL: ±1.5 LSB typical, ±2.5 ...
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AD7631 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. ...
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SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2 5.5 V; VCC = 15 V; VEE = − Table 2. Parameter RESOLUTION ANALOG INPUTS Differential Voltage Range ...
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AD7631 Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time REFERENCE BUFFER REFBUFIN Input Voltage Range EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels V ...
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TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2 5.5 V; VCC = 15 V; VEE = − Table 3. Parameter CONVERSION AND RESET (See Figure 35 and Figure 36) Convert Pulse Width Time ...
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AD7631 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SDCLK First Edge Delay Minimum Internal SDCLK Period Minimum Internal SDCLK Period Maximum Internal SDCLK High Minimum Internal SDCLK Low Minimum SDOUT Valid Setup ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Inputs/Outputs 1 1 IN+ , IN− to AGND VEE − 0 VCC + 0.3 V REF, REFBUFIN, TEMP, AVDD + 0 REFGND to AGND AGND − 0.3 V ...
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AD7631 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D4/DIVSCLK[0] D5/DIVSCLK[1] NOTES 1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Table 6. Pin Function ...
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Pin No. Mnemonic Type Description 11, 12 D[4:5] or DI/O When MODE[1: these pins are Bit 4 and Bit 5 of the parallel port data output bus. DIVSCLK[0:1] When MODE[1: serial data ...
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AD7631 1 Pin No. Mnemonic Type Description 23 D12 or DO When MODE[1: this output is used as Bit 12 of the parallel port data output bus. SYNC When MODE[1: Serial Data Frame ...
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Pin No. Mnemonic Type Description 37 REF AO/I Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing ...
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AD7631 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = − 2 250kSPS POSITIVE INL = 1.15 LSB S NEGATIVE INL = –0.94 LSB 2.0 1.5 ...
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FREQUENCY (kHz) Figure 11. FFT 20 kHz, Bipolar 5 V Range, Internal Reference 100 98 SNR 96 94 SINAD ENOB ...
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AD7631 –104 –108 –112 –116 ±10V –120 –124 0V TO 10V ±5V –128 –132 –55 –35 – TEMPERATURE (°C) Figure 17. THD vs. Temperature ZERO/OFFSET ERROR –4 –8 ...
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PD = PDBUF = PDREF = HIGH 600 500 400 VEE, –15V VCC, +15V DVDD 300 OVDD AVDD 200 100 0 –55 –35 – TEMPERATURE (°C) Figure 23. Power-Down Operating Currents vs. Temperature 50 45 ...
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AD7631 TERMINOLOGY Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is ...
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THEORY OF OPERATION IN+ MSB 131,072C REF REFGND 131,072C 65,536C MSB IN– OVERVIEW The AD7631 is a very fast, low power, precise, 18-bit ADC using successive approximation, capacitive digital-to-analog (CDAC) architecture. The AD7631 can be configured at any time for ...
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AD7631 TRANSFER FUNCTIONS Using the D0/OB/ 2C digital input or via the configuration register, except in 18-bit parallel interface mode, the AD7631 offers two output codings: straight binary and twos complement. See Figure 26 and Table 8 characteristic and digital ...
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ANALOG SUPPLY (5V) 10µF 100nF +7V TO +15.75V SUPPLY 100nF 10µF 100nF 10µF –7V TO –15.75V SUPPLY NOTE 6 C REF 22µF NOTE 4 100nF NOTE 2 ANALOG INPUT+ 15Ω 2.7nF C NOTE 2 ANALOG INPUT– 15Ω U1 ...
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AD7631 The four diodes D4, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this ...
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N is the noise factor of the amplifier (1 in buffer configuration). e and e are the equivalent input voltage noise densities N+ N− of the op amps connected to IN+ and IN−, in nV/√Hz. This approximation can be utilized ...
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AD7631 External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) To use an external reference with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the ...
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Power Sequencing The AD7631 is independent of power supply sequencing and is very insensitive to power supply variations on AVDD over a wide frequency range, as shown in Figure 33 ...
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AD7631 INTERFACES DIGITAL INTERFACE The AD7631 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7631 ...
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Interface (Master or Slave) The 18-bit interface is selected by setting MODE[1: this mode, the data output is straight binary. 16-Bit and 8-Bit Interface (Master or Slave) In the 16-bit (MODE[1: and 8-bit (MODE[1:0] ...
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AD7631 CS, RD CNVST BUSY t 17 SYNC SDCLK t 18 SDOUT Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) CS CNVST BUSY ...
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External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode the most recommended of the serial slave modes. Figure 44 shows the detailed timing diagrams for this method. After a conversion ...
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AD7631 CS BUSY t 31 SDCLK X* SDOUT t 16 SDIN *A DISCONTINUOUS SDCLK IS RECOMMENDED. CS CNVST BUSY t 31 SDCLK X* SDOUT DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 45. Slave Serial Data Timing for Reading (Read ...
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HARDWARE CONFIGURATION The AD7631 can be configured at any time with the dedicated hardware pins BIPOLAR, TEN, D0/OB and PD for parallel mode (MODE[1: serial hardware mode (MODE[1: HW/ SW ...
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AD7631 BIPOLAR = MODE[1: TEN = HW/ CNVST BUSY t 31 SCCS t 31 SCCLK SCIN X BIPOLAR START t 33 MICROPROCESSOR INTERFACING The AD7631 is ...
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APPLICATION INFORMATION LAYOUT GUIDELINES While the AD7631 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Notes Temperature Range AD7631BCPZ −40°C to +85°C AD7631BCPZRL −40°C to +85°C AD7631BSTZ −40°C to +85°C AD7631BSTZRL −40°C to +85°C 2 EVAL-AD7631CBZ 3 EVAL-CONTROL BRD3 RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. ...