4432-T-B1 B 470 Silicon Laboratories Inc, 4432-T-B1 B 470 Datasheet - Page 65

• Manufacturer Part Number: 4432-T-B1 B 470
• Description: RF Modules & Development Tools Tx/Rx Split 4432 TRx Testcard
• Manufacturer: Silicon Laboratories Inc

Specifications of 4432-T-B1 B 470

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4C-4E
6A-6C
50-5F
63-68
Add
3C
3D
6D
7C
7D
31
32
33
34
35
36
37
38
39
3A
3B
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4F
60
61
62
69
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7E
7F
Note: Detailed register descriptions are available in “AN440: EZRadioPRO Detailed Register Descriptions.”
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
Frequency Hopping Step Size
Crystal Oscillator/Control Test
Nominal Carrier Frequency 1
Nominal Carrier Frequency 0
Frequency Hopping Channel
Preamble Detection Control
Modulation Mode Control 1
Modulation Mode Control 2
Channel Filter Coefficient
Received Packet Length
Transmit Packet Length
Frequency Band Select
Frequency Deviation
Received Header 3
Received Header 2
Received Header 1
Received Header 0
Frequency Offset 1
Frequency Offset 2
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
TX FIFO Control 1
TX FIFO Control 2
Header Control 1
Header Control 2
Preamble Length
Header Enable 3
Header Enable 2
Header Enable 1
Header Enable 0
RX FIFO Control
Check Header 3
Check Header 2
Check Header 1
Check Header 0
AGC Override 1
Function/Desc
TX Data Rate 1
TX Data Rate 0
EzMAC status
ADC8 Control
Sync Word 3
Sync Word 2
Sync Word 1
Sync Word 0
FIFO Access
TX Power
Address
Select
Inv_pre_th[3]
Table 18. Register Descriptions (Continued)
prealen[7]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
preath[4]
hden[31]
hden[23]
hden[15]
sync[31]
sync[23]
sync[15]
chhd[31]
chhd[23]
chhd[15]
rxplen[7]
txhd[31]
txhd[23]
txhd[15]
pklen[7]
rxhd[31]
rxhd[23]
rxhd[15]
skipsyn
hden[7]
txdr[15]
sync[7]
chhd[7]
pwst[2]
txhd[7]
rxhd[7]
fhch[7]
fifod[7]
txdr[7]
trclk[1]
fc[15]
fhs[7]
fd[7]
fo[7]
fc[7]
D7
0
Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0]
prealen[6]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
preath[3]
hden[30]
hden[22]
hden[14]
sync[30]
sync[22]
sync[14]
chhd[30]
chhd[22]
chhd[14]
rxplen[6]
hdlen[2]
txhd[30]
txhd[22]
txhd[14]
pklen[6]
rxhd[30]
rxhd[22]
rxhd[14]
hden[6]
txdr[14]
sync[6]
chhd[6]
pwst[1]
txhd[6]
rxhd[6]
fhch[6]
fifod[6]
txdr[6]
trclk[0]
rxcrc1
fc[14]
fhs[6]
sbsel
fd[6]
fo[6]
fc[6]
D6
sgi
bcen[3:0]
Rev 1.1
txdtrtscale
prealen[5]
preath[2]
Reserved
Reserved
txaethr[5]
chhd[29]
chhd[21]
chhd[13]
hden[29]
hden[21]
hden[13]
rxplen[5]
dtmod[1]
txafthr[5]
rxafthr[5]
sync[29]
sync[21]
sync[13]
rxhd[29]
rxhd[21]
rxhd[13]
hdlen[1]
txhd[29]
txhd[21]
txhd[13]
pklen[5]
chhd[5]
hden[5]
adc8[5]
txdr[13]
sync[5]
rxhd[5]
pwst[0]
pksrch
txhd[5]
fhch[5]
fifod[5]
agcen
txdr[5]
hbsel
fc[13]
fhs[5]
fd[5]
fo[5]
fc[5]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D5
enphpwdn
prealen[4]
Reserved
Reserved
txaethr[4]
preath[1]
chhd[28]
chhd[20]
chhd[12]
hden[28]
hden[20]
hden[12]
rxplen[4]
dtmod[0]
txafthr[4]
rxafthr[4]
sync[28]
sync[20]
sync[12]
rxhd[28]
rxhd[20]
rxhd[12]
hdlen[0]
txhd[28]
txhd[20]
txhd[12]
pklen[4]
chhd[4]
hden[4]
adc8[4]
txdr[12]
sync[4]
lnagain
txhd[4]
rxhd[4]
clkhyst
fhch[4]
fifod[4]
txdr[4]
fc[12]
fhs[4]
pkrx
fd[4]
fo[4]
fb[4]
fc[4]
D4
Data
prealen[3]
chfiladd[3]
Reserved
txaethr[3]
preath[0]
hden[27]
hden[19]
enbias2x
rxafthr[3]
sync[27]
sync[19]
chhd[27]
chhd[19]
chhd[11]
hden[11]
rxplen[3]
manppol
txafthr[3]
sync[11]
txhd[27]
txhd[19]
rxhd[27]
rxhd[19]
rxhd[11]
fixpklen
txhd[11]
pklen[3]
hden[3]
sync[3]
chhd[3]
adc8[3]
Ina_sw
txdr[11]
pkvalid
txhd[3]
rxhd[3]
fhch[3]
fifod[3]
txdr[3]
fhs[3]
eninv
fc[11]
pga3
fd[3]
fo[3]
fb[3]
fc[3]
D3
Si4430/31/32-B1
chfiladd[2]
synclen[1]
prealen[2]
rssi_off[2]
enmaninv
Reserved
txaethr[2]
enamp2x
chhd[26]
chhd[18]
chhd[10]
hden[26]
hden[18]
hden[10]
rxplen[2]
txafthr[2]
rxafthr[2]
crcerror
sync[26]
sync[18]
sync[10]
rxhd[26]
rxhd[18]
txpow[2]
txhd[26]
txhd[18]
txhd[10]
pklen[2]
rxhd[10]
chhd[2]
hden[2]
adc8[2]
txdr[10]
sync[2]
txhd[2]
rxhd[2]
fhch[2]
fifod[2]
txdr[2]
fc[10]
fhs[2]
pga2
fd[8]
fd[2]
fo[2]
fb[2]
fc[2]
D2
hdch[3:0]
synclen[0]
prealen[1]
chfiladd[1]
rssi_off[1]
modtyp[1]
enmanch
txaethr[1]
hden[25]
hden[17]
rxafthr[1]
sync[25]
sync[17]
chhd[25]
chhd[17]
rxplen[1]
txpow[1]
txafthr[1]
txhd[25]
txhd[17]
rxhd[25]
rxhd[17]
pklen[1]
hden[9]
hden[1]
sync[9]
sync[1]
chhd[9]
chhd[1]
adc8[1]
txhd[9]
txhd[1]
rxhd[9]
rxhd[1]
fhch[1]
fifod[1]
bufovr
txdr[9]
txdr[1]
fhs[1]
pga1
fd[1]
fo[1]
fo[9]
fb[1]
fc[1]
pktx
fc[9]
D1
prealen[0]
chfiladd[0]
prealen[8]
rssi_off[0]
modtyp[0]
txaethr[0]
hden[24]
hden[16]
rxafthr[0]
chhd[24]
chhd[16]
rxplen[0]
txafthr[0]
sync[24]
sync[16]
txhd[24]
txhd[16]
rxhd[24]
rxhd[16]
txpow[0]
pklen[0]
enwhite
chhd[8]
chhd[0]
hden[8]
hden[0]
adc8[0]
sync[8]
sync[0]
rxhd[8]
rxhd[0]
pksent
txhd[8]
txhd[0]
fhch[0]
fifod[0]
txdr[8]
txdr[0]
enbuf
fhs[0]
pga0
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
fc[0]
D0
65
Default
POR
0Ch
2Dh
D4h
3Dh
0Ch
BBh
22h
08h
2Ah
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
10h
00h
24h
20h
18h
0Ah
20h
00h
00h
75h
80h
00h
00h
37h
04h
37h
00h
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