4432-T-B1 B 470 Silicon Laboratories Inc, 4432-T-B1 B 470 Datasheet - Page 43

• Manufacturer Part Number: 4432-T-B1 B 470
• Description: RF Modules & Development Tools Tx/Rx Split 4432 TRx Testcard
• Manufacturer: Silicon Laboratories Inc

Specifications of 4432-T-B1 B 470

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field before
returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the FIFO the
microcontroller needs to command the chip to re-enter TX mode. Figure 19 provides an example transaction where
the packet length is set to three bytes.
6.4. Packet Handler RX Mode
6.4.1. Packet Handler Disabled
When the packet handler is disabled certain fields in the received packet are still required. Proper modem
operation requires preamble and sync when the FIFO is being used, as shown in Figure 20. Bits after sync will be
treated as raw data with no qualification. This mode allows for the creation of a custom packet handler when the
automatic qualification parameters are not sufficient. Manchester encoding is supported but data whitening, CRC,
and header checks are not.
6.4.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. Register contents
are used to construct the header field and length information encoded into the transmitted packet when
transmitting. The receive FIFO can be configured to handle packets of fixed or variable length with or without a
header. If multiple packets are desired to be stored in the FIFO, then there are options available for the different
fields that will be stored into the FIFO. Figure 21 demonstrates the options and settings available when multiple
packets are enabled. Figure 22 demonstrates the operation of fixed packet length and correct/incorrect packets.
Figure 20. Required RX Packet Structure with Packet Handler Disabled
Preamble
Register
Register
Data
Data
Transmission:
Figure 21. Multiple Packets in RX Packet Handler
Figure 19. Multiple Packets in TX Packet Handler
H
L
Data
FIFO
ength
eader(s)
D ata 1
D ata 2
D ata 3
D ata 4
D ata 5
D ata 6
D ata 7
D ata 8
D ata 9
}
}
}
SYNC
This w ill be sent in the first transm ission
This w ill be sent in the second transm ission
This w ill be sent in the third transm ission
Rev 1.1
rx_multi_pk_en = 0
Data
RX FIFO Contents:
Data
txhdlen = 0
L
0
fixpklen
rx_multi_pk_en = 1
DATA
Data
Si4430/31/32-B1
1
Data
txhdlen > 0
H
L
0
fixpklen
Data
1
H
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