4432-T-B1 B 470 Silicon Laboratories Inc, 4432-T-B1 B 470 Datasheet - Page 59

• Manufacturer Part Number: 4432-T-B1 B 470
• Description: RF Modules & Development Tools Tx/Rx Split 4432 TRx Testcard
• Manufacturer: Silicon Laboratories Inc

Specifications of 4432-T-B1 B 470

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.8. GPIO Configuration
Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control,
Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode
all the GPIO pads are pulled low.
Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess current con-
The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default
setting. The default settings for each GPIO are listed below:
For a complete list of the available GPIO's see “AN440: EZRadioPRO Detailed Register Descriptions”.
The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive
strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the
drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive
may contribute to increased spurious emissions.
Pin 6, ANT may be used as an alternate to control a TR switch. Pin 6 is a hardwired version of GPIO setting 11000,
Antenna 2 Switch used for antenna diversity. It can be manually controlled by the antdiv[2:0] bits in register 08h if
antenna diversity is not used. See AN440, register 08h for more details.
Add R/W Function/Des
0B
0C
0D
0E
sumption.
R/W
R/W
R/W
R/W
Configuration
Configuration
Configuration
Configuration
cription
I/O Port
GPIO0
GPIO1
GPIO2
gpio0drv[1] gpio0drv[0]
gpio1drv[1] gpio1drv[0]
gpio2drv[1] gpio2drv[0]
D7
GPIO0
GPIO1
GPIO2
GPIO
extitst[2]
D6
extitst[1] extitst[0]
pup0
pup1
pup2
Rev 1.1
D5
00000—Default Setting
Microcontroller Clock
gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0]
gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0]
gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0]
POR Inverted
D4
POR
itsdo
D3
Si4430/31/32-B1
dio2
D2
dio1
D1
dio0
D0
POR Def.
00h
00h
00h
00h
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