4432-T-B1 B 470 Silicon Laboratories Inc, 4432-T-B1 B 470 Datasheet - Page 64

• Manufacturer Part Number: 4432-T-B1 B 470
• Description: RF Modules & Development Tools Tx/Rx Split 4432 TRx Testcard
• Manufacturer: Silicon Laboratories Inc

Specifications of 4432-T-B1 B 470

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Add
0C
0D
1C
1D
2C
2D
00
01
02
03
04
05
06
07
08
09
0A
0B
0E
0F
10
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2E
2F
30
11
Si4430/31/32-B1
12. Register Table and Descriptions
64
R/W
R/W
R/W
R/W Operating & Function Control 1
R/W Operating & Function Control 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Low-Duty Cycle Mode Duration
R/W Low Battery Detector Threshold
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
Clock Recovery Oversampling
Received Signal Strength Indi-
AFC Loop Gearshift Override
Clock Recovery Timing Loop
Clock Recovery Timing Loop
Antenna Diversity Register 1
Antenna Diversity Register 2
Microcontroller Output Clock
ADC Sensor Amplifier Offset
Temperature Sensor Control
Temperature Value Offset
Clock Recovery Gearshift
RSSI Threshold for Clear
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Clock Recovery Offset 2
Clock Recovery Offset 1
Clock Recovery Offset 0
Wake-Up Timer Value 1
Wake-Up Timer Value 2
Crystal Oscillator Load
I/O Port Configuration
OOK Counter Value 1
OOK Counter Value 2
Battery Voltage Level
AFC Correction Read
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
Data Access Control
AFC Timing Control
ADC Configuration
IF Filter Bandwidth
Interrupt Enable 1
Interrupt Enable 2
Channel Indicator
Interrupt Status 1
Interrupt Status 2
Slicer Peak Hold
Function/Desc
Device Version
Device Status
Device Type
Capacitance
AFC Limiter
ADC Value
Override
Gain 1
Gain 0
Ratio
cator
dwn3_bypass
swait_timer[1]
adcstart/adc-
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
afc_corr[9]
afc_corr[9]
tsrange[1]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adrssi1[7]
adrssib[7]
Reserved
ookcnt[7]
rxosr[10]
enswdet
antdiv[2]
ncoff[15]
crgain[7]
Afclim[7]
tvoffs[7]
wtm[15]
rssith[7]
enpacrx
rxosr[7]
xtalshft
wtv[15]
ncoff[7]
wtm[7]
iswdet
enfferr
swres
adc[7]
wtv[7]
rssi[7]
afcbd
done
ldc[7]
ffovfl
ifferr
D7
0
0
0
Table 18. Register Descriptions
swait_timer[0]
gpio1drv[0]
gpio2drv[0]
gpio0drv[0]
afc_corr[8]
afc_corr[9]
enpreaval
tsrange[0]
entxffafull
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adrssia[6]
adrssib[6]
ookcnt[6]
adcsel[2]
antdiv[1]
extitst[2]
ncoff[14]
crgain[6]
Afclim[6]
attack[2]
ipreaval
wtm[14]
ndec[2]
rssith[6]
itxffafull
tvoffs[6]
rxosr[6]
rxosr[9]
wtv[14]
ncoff[6]
wtm[6]
adc[6]
wtv[6]
rssi[6]
lsbfrst
enlbd
enafc
xlc[6]
ldc[6]
ffunfl
D6
0
0
0
Rev 1.1
enpreainval
afcgearh[2]
afc_corr[7]
entxffaem
adrssia[5]
adrssib[5]
ipreainval
Reserved
Reserved
Reserved
Reserved
adcsel[1]
ookcnt[5]
antdiv[0]
ncoff[13]
crgain[5]
Afclim[5]
ookfrzen
attack[1]
extitst[1]
shwait[2]
crcdonly
itxffaem
entsoffs
tvoffs[5]
wtm[13]
ndec[1]
crfast[2]
rssith[5]
rxosr[5]
rxosr[8]
ncoff[5]
wtv[13]
wtm[5]
rxffem
adc[5]
clkt[1]
wtv[5]
rssi[5]
xlc[5]
ldc[5]
pup0
pup1
pup2
enwt
Reserved
D5
0
0
0
afcgearh[1]
rxncocomp
afc_corr[6]
peakdeten
enrxffafull
adrssia[4]
adrssib[4]
Reserved
adcsel[0]
ookcnt[4]
ncoff[12]
crgain[4]
Afclim[4]
extitst[0]
shwait[1]
attack[0]
headerr
gpio0[4]
gpio1[4]
gpio2[4]
entstrim
tvoffs[4]
wtm[12]
ndec[0]
crfast[1]
rssith[4]
irxffafull
x32ksel
rxosr[4]
ncoff[4]
skip2ph
wtv[12]
stallctrl
wtm[4]
vbat[4]
rxmpk
adc[4]
enrssi
clkt[0]
wtv[4]
lbdt[4]
rssi[4]
wtr[4]
ldc[4]
xlc[4]
vc[4]
dt[4]
irssi
D4
Data
afcgearh[0] 1p5 bypass
afc_corr[5]
adcoffs[3]
adrssia[3]
adrssib[3]
reserved
adcref[1]
madeten
ookcnt[3]
ncoff[19]
ncoff[11]
crgain2x
crgain[3]
Afclim[3]
decay[3]
gpio0[3]
gpio1[3]
gpio2[3]
tstrim[3]
shwait[0]
crfast[0]
tvoffs[3]
wtm[11]
rxosr[3]
rssith[3]
enpactx
ncoff[3]
wtv[11]
vbat[3]
wtm[3]
filset[3]
enwut
autotx
adc[3]
wtv[3]
lbdt[3]
rssi[3]
enext
xlc[3]
wtr[3]
ldc[3]
vc[3]
enlfc
itsdo
dt[3]
txon
iwut
iext
D3
afc_corr[4]
ookcnt[10]
crgain[10]
adrssia[2]
adrssib[2]
adcoffs[2]
enpksent
ookcnt[2]
reserved
adcref[0]
crslow[2]
ncoff[18]
ncoff[10]
crgain[2]
Afclim[2]
decay[2]
anwait[2]
gpio0[2]
gpio1[2]
gpio2[2]
tstrim[2]
tvoffs[2]
wtm[10]
rssith[2]
rxosr[2]
ncoff[2]
ipksent
mclk[2]
wtv[10]
wtm[2]
vbat[2]
enldm
adc[2]
lbdt[2]
filset[2]
wtv[2]
rssi[2]
enlbd
xlc[2]
wtr[2]
ldc[2]
encrc
vc[2]
dt[2]
rxon
dio2
ilbd
D2
adcgain[1]
afc_corr[3]
enpkvalid
enchiprdy
adcoffs[1]
adrssia[1]
adrssib[1]
ookcnt[9]
ookcnt[1]
crslow[1]
anwait[1]
ncoff[17]
crgain[9]
crgain[1]
Afclim[1]
decay[1]
gpio0[1]
gpio1[1]
gpio2[1]
tstrim[1]
ichiprdy
tvoffs[1]
rxosr[1]
rssith[1]
ipkvalid
mclk[1]
ncoff[9]
ncoff[1]
vbat[1]
wtm[9]
wtm[1]
filset[1]
cps[1]
adc[1]
wtv[9]
wtv[1]
lbdt[1]
matap
rssi[1]
ffclrrx
wtr[1]
crc[1]
xlc[1]
ldc[1]
vc[1]
pllon
dt[1]
dio1
D1
afc_corr[2]
encrcerror
adcgain[0]
adcoffs[0]
adrssia[0]
adrssib[0]
crslow[0]
ookcnt[8]
ookcnt[0]
ncoff[16]
crgain[8]
crgain[0]
Afclim[0]
decay[0]
icrcerror
gpio0[0]
gpio1[0]
gpio2[0]
anwait[0]
tstrim[0]
tvoffs[0]
ph0size
rssith[0]
rxosr[0]
ncoff[8]
ncoff[0]
mclk[0]
wtm[8]
wtm[0]
vbat[0]
filset[0]
cps[0]
adc[0]
lbdt[0]
rssi[0]
enpor
wtv[8]
wtv[0]
ffclrtx
xlc[0]
wtr[0]
ldc[0]
crc[0]
vc[0]
dt[0]
xton
dio0
ipor
D0
Default
00111
POR
AEh
BCh
8Dh
06h
00h
03h
01h
00h
7Fh
06h
00h
00h
00h
00h
00h
00h
20h
00h
03h
00h
01h
00h
14h
01h
40h
0Ah
03h
64h
01h
47h
02h
8Fh
1Eh
00h
18h
26h
00h
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