Si5355-EVB Silicon Laboratories Inc, Si5355-EVB Datasheet - Page 6

• Manufacturer Part Number: Si5355-EVB
• Description: Clock & Timer Development Tools Si5355 custom clk eval board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5355-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5355
6
Table 4. AC Characteristics
(V
Input Clock
Clock Input Frequency
Clock Input Rise/Fall Time
Clock Input Duty Cycle
Clock Input Capacitance
Output Clocks
Clock Output Frequency
Clock Output Frequency Synthesis
Resolution
Output Load Capacitance
Clock Output Rise/Fall Time
Clock Output Rise/Fall Time
Clock Output Duty Cycle
Powerup Time
Output Enable Time
Output Transition Time
Reset Minimum Pulse Width
Output-Output Skew
CLKIN Loss of Signal Assert Time
CLKIN Loss of Signal Deassert
Time
POR to Output Clock Valid
Period Jitter
Cycle-Cycle Jitter
Note: Measured in accordance to
Phase Jitter
PLL Loop Bandwidth
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
Jedec Standard 65.
Parameter
Symbol
T
T
J
T
t
J
T
T
T
F
LOS_b
TRANS
RESET
PPKPK
t
t
F
T
T
SKEW
CCPK
J
DC
C
DC
F
R
R
R
LOS
RDY
F
C
RES
BW
OE
PH
PU
IN
/T
/T
/T
IN
O
L
A
F
F
F
= –40 to 85 °C)
See "3.3. Input and Output
Frequency Configuration"
POR to output clock valid
After falling edge of reset
frequency, f
Rev. 0.3
12 kHz to 20 MHz
Outputs at same
Test Condition
20 to 80% V
20 to 80% V
20 to 80% V
10000 cycles
10000 cycles
on page 11
C
< 2 ns tr/tf
C
L
L
= 15 pF
= 2 pF
OUT
> 5 MHz
DD
DD
DD
,
,
–150
0.01
Min
40
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
1
0.45
Typ
2.6
0.2
1.6
15
50
50
40
—
—
—
—
—
—
—
—
—
—
—
—
2
2
+150
Max
0.85
200
200
200
1.7
60
55
10
75
70
—
—
—
—
2
0
2
2
5
1
2
ps pk-pk
ps rms
Units
ps pk
MHz
MHz
MHz
ppm
ms
ms
ms
pF
pF
ns
ns
ns
µs
ns
ps
µs
µs
%
%