Si5355-EVB Silicon Laboratories Inc, Si5355-EVB Datasheet - Page 19

• Manufacturer Part Number: Si5355-EVB
• Description: Clock & Timer Development Tools Si5355 custom clk eval board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5355-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Recommended PCB Layout
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no more
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is
allowed if more vias are used to keep the inductance from increasing.
to be 60 µm minimum, all the way around the pad.
paste release.
Dimension
P1
P2
X1
Y1
C1
C2
E
Table 10. PCB Land Pattern
2.50
2.50
0.20
0.75
Min
Rev. 0.3
3.90
3.90
0.50
Nom
2.55
2.55
0.25
0.80
Max
2.60
2.60
0.30
0.85
Si5355
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