Si5355-EVB Silicon Laboratories Inc, Si5355-EVB Datasheet

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Si5355-EVB

Manufacturer Part Number
Si5355-EVB
Description
Clock & Timer Development Tools Si5355 custom clk eval board
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of Si5355-EVB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
A
8-O
Features
Applications
Description
The Si5355 is a highly flexible clock generator capable of synthesizing four
completely non-integer related frequencies up to 200 MHz. The device has four
banks of outputs with each bank supporting two CMOS outputs at the same
frequency. Using Silicon Laboratories' patented MultiSynth fractional divider
technology, all outputs are guaranteed to have 0 ppm frequency synthesis error
regardless of configuration, enabling the replacement of multiple clock ICs and
crystal oscillators with a single device. Through a flexible web configuration utility
called ClockBuilder™ (www.silabs.com/ClockBuilder), factory-customized pin-
controlled Si5355 devices are available in two weeks without minimum order
quantity restrictions. The Si5355 supports up to three independent, pin-selectable
device configurations, enabling one device to replace three separate clock ICs.
Functional Block Diagram
Rev. 0.3 9/10
Generates any frequency from 1 to
200 MHz on each of the 4 output banks
Guaranteed 0 ppm frequency synthesis
error for any combination of frequencies
25 or 27 MHz xtal or 5–200 MHz input clk
Eight CMOS clock outputs
Five programmable control pins (output
enable, frequency select, reset)
Separate OEB pins to disable individual
banks or all outputs
Loss of signal output
Low 50 ps (typ) pk-pk period jitter
Phase jitter: 2 ps rms 12 kHz–20 MHz
Printers
Audio/video
Networking
Communications
N Y
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
UTPUT
- F
REQUENCY
C
LOCK
1–200 MH
Copyright © 2010 by Silicon Laboratories
G
E N E RA TO R
Storage
Switches/routers
Computing
Servers
OC-3/OC-12 line cards
Excellent PSRR performance
eliminates need for external power
supply filtering
Low power: 45 mA
Core VDD: 1.8, 2.5, or 3.3 V
Separate VDDO for each bank of
outputs: 1.8, 2.5, or 3.3 V
Small size: 4x4 mm 24-QFN
Industrial temperature range:
–40 to +85 °C
Custom versions available using
ClockBuilder™ web utility
Samples available in 2 weeks
Z
Q
UAD
F
REQUENCY
CLKIN
CLKIN
XA
XA
XB
XB
P1
P1
P4
P4
P5
P5
1
1
2
2
3
3
4
4
5
5
6
6
Ordering Information:
7
7
24
24
Pin Assignments
See page 20.
23
23
8
8
Top View
Top View
Si5355
9
9
22
22
GND
GND
GND
GND
10
10
21
21
11
11
20
20
12
12
19
19
18
18
17
17
16
16
15
15
14
14
13
13
CLK2
CLK2
CLK3
CLK3
VDDOC
VDDOC
CLK4
CLK4
CLK5
CLK5
VDDOB
VDDOB
Si5355

Related parts for Si5355-EVB

Si5355-EVB Summary of contents

Page 1

... Communications  Description The Si5355 is a highly flexible clock generator capable of synthesizing four completely non-integer related frequencies up to 200 MHz. The device has four banks of outputs with each bank supporting two CMOS outputs at the same frequency. Using Silicon Laboratories' patented MultiSynth fractional divider ...

Page 2

... Si5355 2 Rev. 0.3 ...

Page 3

... Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.8. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Pin Descriptions—Si5355 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rev ...

Page 4

... Si5355 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10 Parameter Ambient Temperature Core Supply Voltage Output Buffer Supply Voltage Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted ...

Page 5

... V CLKIN, P1, P2 OEB, pins (P4, P5) V CLKIN, P1, P2 P4,P5 V Pins: CLK0 – Pins: CLK0 Pin: LOS OLLOS Rev. 0.3 Si5355 Min Typ Max Units — 0 — 3.63 DD 0.85 — 1.2 –0.2 — 0 — — 0.3 V – 0.3 — — DDO — — ...

Page 6

... Si5355 Table 4. AC Characteristics (V = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10 Parameter Input Clock Clock Input Frequency Clock Input Rise/Fall Time Clock Input Duty Cycle Clock Input Capacitance Output Clocks Clock Output Frequency Clock Output Frequency Synthesis Resolution Output Load Capacitance Clock Output Rise/Fall Time ...

Page 7

... Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Test Condition Option 1 F XTAL Option < 30 MHz ESR < 90  Symbol Test Condition Theta JA Theta JC Rev. 0.3 Si5355 Min Typ Max Units — 25 — MHz — 27 — MHz — — 100 — ...

Page 8

... Processor 23 PAD 23 PAD Ethernet PHY 125 MHz XB 22 CLK0 CLKIN 21 x CLK1 48 MHz 18 CLK2 17 x CLK3 14 CLK4 Si5355 13 x CLK5 10 LOS CLK6 9 x CLK7 P1 P2 35.788 MHz P3 P4 Touchscreen P5 PAD 23 23 PAD Rev. 0.3 25 MHz Ethernet 25 MHz Ethernet PHY Ethernet 25 MHz ...

Page 9

... ClockBuilder. If the crystal input option is used, the Si5355 operates as a free-running clock generator. In this mode of operation the device requires a low-cost MHz fundamental mode crystal connected across XA and XB as shown in Figure 2. Given the Si5355’s frequency flexibility, the same MHz crystal can be reused to generate any combination of output frequencies. Custom frequency crystals are not required. The Si5355 integrates the crystal load capacitors on-chip to reduce external component count ...

Page 10

... Next-generation timing architectures require a wide range of frequencies which are often non-integer related. Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete XOs, often at the expense of BOM complexity and power. The Si5355 uses patented MultiSynth technology to dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (PLLs single device, greatly minimizing size and power requirements versus traditional solutions ...

Page 11

... Multi-Function Control Inputs The Si5355 supports 5 user-defined input pins (pins 12, 19) that are customizable to support the functions listed below. The pinout of each device is customized using the ClockBuilder utility. This enables the device to be custom tailored to a specific application. Each of the different functions is described in further detail below. ...

Page 12

... OEB_45 and OEB_67, respectively. Alternatively, all clock outputs can be disabled using the master output enable OEB_all. When a Si5355 clock output bank is disabled, both outputs are driven to an active low state. When one or more banks of clock outputs are enabled or disabled, clock start and stop transitions are handled glitchlessly. ...

Page 13

... CMOS Output Drivers The Si5355 has 4 banks of outputs with each bank comprised of 2 clocks for a total of 8 CMOS outputs per device. Each of the output banks can operate from a different VDDO supply (1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply applications. All clock outputs between 1 and 200 MHz are in-phase to within ±150 ps. When an output bank is disabled using any of the OEB functions, the clock outputs are stopped low. The CMOS output driver has a controlled impedance in the range  ...

Page 14

... Power Supply Considerations The Si5355 has 2 core supply voltage pins (V enabling the device to be used in mixed supply applications. The Si5355 does not require ferrite beads for power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter ...

Page 15

... This pin functions as a high-impedance input for CMOS clock signals. The input should be dc coupled crystal is used as the device frequency reference, this pin should be tied to GND. Top View GND GND Table 8. Si5355 Pin Descriptions Description Rev. 0.3 Si5355 18 CLK2 17 CLK3 16 VDDOB 15 VDDOC 14 CLK4 13 CLK5 15 ...

Page 16

... Si5355 Table 8. Si5355 Pin Descriptions (Continued Multi-Function Input. This pin functions as a multi-function input pin. The pin function (OEB_all, OEB_01, OEB_23, OEB_45, OEB_67, or Reset) is user-selectable at time of configuration using the ClockBuilder configuration utility. A resistor voltage divider is recommended when controlled by a signal greater than 1.2 V. See “2. Typical Application Circuit” for details. ...

Page 17

... Table 8. Si5355 Pin Descriptions (Continued) 18 CLK2 O Output Clock 2. CMOS output clock. If unused, this pin must be left floating Multi-Function Input. This pin functions as a multi-function input pin. The pin function (OEB_all, OEB_01, OEB_23, OEB_45, OEB_67, Frequency Select, or Reset) is user-selectable at time of configuration using the ClockBuilder configuration utility ...

Page 18

... Si5355 5. Package Outline: 24-Lead QFN Figure 7. 24-Lead Quad Flat No-Lead (QFN) Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. ...

Page 19

... A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Table 10. PCB Land Pattern Min Nom 2.50 2.55 2.50 2.55 0.20 0.25 0.75 0.80 3.90 3.90 0.50 Rev. 0.3 Si5355 Max 2.60 2.60 0.30 0.85 19 ...

Page 20

... Si5355A Any-Frequency 1–200 MHz Quad Frequency 8-Output Clock Generator 20 www.silabs.com/ClockBuilder Axxxxx Rev. 0.3 to specify a unique Si5355 R = tape & reel Blank = tubes M = RoHS6, Pb-free QFN – product revision xxxxx = 5-digit custom code assigned to each unique device configuration by ClockBuilder ...

Page 21

... Changed period jitter specification from 100 ps to  pk-pk. Added Theta JC specification to Table 6 on page 7.  Updated "2. Typical Application Circuit" on page 8.  Added Table 7 on page 10.  Clarified device operation during an input clock loss  of signal. Updated Recommended PCB Layout.  Rev. 0.3 Si5355 21 ...

Page 22

... Si5355 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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