Si5355-EVB Silicon Laboratories Inc, Si5355-EVB Datasheet - Page 14

• Manufacturer Part Number: Si5355-EVB
• Description: Clock & Timer Development Tools Si5355 custom clk eval board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5355-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5355
3.9. Jitter Performance
The Si5355 provides consistently low jitter for any combination of output frequencies. The device leverages a low
phase noise single PLL architecture and Silicon Laboratories’ patented MultiSynth fractional output divider
technology to deliver period jitter less than 50 ps pk-pk (typ) for any output frequency plan. This level of jitter
performance is guaranteed across process, temperature, and voltage. The Si5355 provides superior performance
to conventional multi-PLL solutions which may suffer from degraded jitter performance depending on frequency
plan and the number of active PLLs.
3.10. Power Supply Considerations
The Si5355 has 2 core supply voltage pins (V
enabling the device to be used in mixed supply applications. The Si5355 does not require ferrite beads for power
supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power supply
noise on output jitter. Figure 6 shows that the additive jitter created when a significant amount of noise is applied to
the device power supply is very small.
3.11. ClockBuilder Web-Customization Utility
ClockBuilder is a web-based utility available at
tailor the Si5355’s flexible clock architecture to meet any application-specific requirements and order custom clock
samples. Through a simple point-and-click interface, users can specify any combination of input frequency and
output frequencies and generate a custom part number for each application-specific configuration. In addition to
creating part numbers, this utility can be used to order samples and place production orders. There are no
minimum order quantity restrictions.
ClockBuilder enables mass customization of clock generators. This allows a broader range of applications to take
advantage of using application-specific pin controlled clocks, simplifying design while eliminating the firmware
development required by traditional I
Based on Silicon Labs’ patented MultiSynth technology, the device PLL output frequency is constant and all clock
output frequencies are synthesized by the four MultiSynth fractional dividers. All PLL parameters, including divider
settings, VCO frequency, loop bandwidth, charge pump current, and phase margin are internally set by the device
during the configuration process. This ensures optimized jitter performance and loop stability while simplifying
design.
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Figure 6. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply
10
9
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1
0
0.0001
2
C-programmable clock generators.
0.001
Modulation Frequency (MHz)
DD
www.silabs.com/ClockBuilder
) and 4 clock output bank supply voltage pins (V
Rev. 0.3
0.01
0.1
that allows hardware designers to
VDDO
VDD
1
DDOA
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DDOD
),