Si5355-EVB Silicon Laboratories Inc, Si5355-EVB Datasheet - Page 10

• Manufacturer Part Number: Si5355-EVB
• Description: Clock & Timer Development Tools Si5355 custom clk eval board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5355-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5355
Control input signals to P4 and P5 cannot exceed 1.2 V, yet also must meet the V
outlined in Table 3 on page 5. When these inputs are driven from CMOS sources, a resistive attenuator as shown
in the Typical Application Circuits must be used. Suggested standard 1% resistor values for Rse and Rsh are show
in Table 7.
3.2. Breakthrough MultiSynth Technology
Next-generation timing architectures require a wide range of frequencies which are often non-integer related.
Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete XOs,
often at the expense of BOM complexity and power. The Si5355 uses patented MultiSynth technology to
dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops
(PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions. Based on a
fractional-N PLL, the heart of the architecture is a low phase noise, high-frequency VCO. The VCO supplies a high
frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth
operates as a high-speed fractional divider with Silicon Laboratories' proprietary phase error correction to divide
down the VCO clock to the required output frequency with very low jitter.
The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two
closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase
error generated by this process, MultiSynth calculates the relative phase difference between the clock produced by
the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock
waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter
performance. Based on this architecture, the output of each MultiSynth can produce any frequency from 1 to
200 MHz.
10
f
VCO
Figure 4. Silicon Labs' MultiSynth Technology
CMOS Level
Divider Select
(DIV1, DIV2)
Fractional-N
1.8 V
2.5 V
3.3 V
Divider
Table 7. 1% Resistor Values
Rse ()
1000
1960
3090
MultiSynth
Rev. 0.3
Phase Error
Calculator
Rsh ()
1580
1580
1580
Adjust
Phase
OH
and V
f
OUT
OL
specifications