Si5355-EVB Silicon Laboratories Inc, Si5355-EVB Datasheet - Page 11

• Manufacturer Part Number: Si5355-EVB
• Description: Clock & Timer Development Tools Si5355 custom clk eval board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5355-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3. Input and Output Frequency Configuration
The Si5355 utilizes a single PLL-based architecture, four independent MultiSynth fractional output dividers, and a
MultiSynth fractional feedback divider such that a single device provides the clock generation capability of 4
independent PLLs. Unlike competitive multi-PLL solutions, the Si5355 can generate four unique non-integer
related output frequencies with 0 ppm frequency error for any combination of output frequencies. In addition, any
combination of output frequencies can be generated from a single reference frequency without having to change
the crystal or reference clock frequency between frequency configurations.
The Si5355 frequency configuration is set when the device configuration is specified using the ClockBuilder web-
based utility available at www.silabs.com/ClockBuilder. Any combination of output frequencies ranging from 1 to
200 MHz can be configured on each of the device outputs. Up to three unique device configurations can be
specified in a single device, enabling the Si5355 to replace 3 different clock generators.
The following equation governs how the output frequency is calculated.
where f
is the MultiSynth output divider value and f
feedback dividers are fractional dividers expressed in terms of an integer and a fraction. The integer portion has
10-bit resolution and the fractional portion has 30-bit resolution in both the numerator and denominator, meaning
that, for all practical purposes, any output frequency can be defined exactly from the input frequency with exact
(0 ppm) frequency synthesis error.
3.4. Multi-Function Control Inputs
The Si5355 supports 5 user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the functions
listed below. The pinout of each device is customized using the ClockBuilder utility. This enables the device to be
custom tailored to a specific application. Each of the different functions is described in further detail below.
IN
Pin Function
is the reference frequency, N is the MultiSynth feedback divider value, P is the reference divider value, M
OEB_01
OEB_23
OEB_45
OEB_67
OEB_all
RESET
FS0
FS1
Output Enable All.
All outputs enabled when low.
Output Enable Bank A.
CLK0/1 enabled when low.
Output Enable Bank B.
CLK2/3 enabled when low.
Output Enable Bank C.
CLK4/5 enabled when low.
Output Enable Bank D.
CLK6/7 enabled when low.
Frequency Select.
Selects active device frequency plan from factory-
configured profiles.
Frequency Select.
Selects active device frequency plan from factory-
configured profiles.
Reset.
Device reset required to change FS[1:0] pin setting.
OUT
Description
f
is the resulting output frequency. The MultiSynth output and
OUT
Rev. 0.3
=
f
---------------- -
P M
IN


N
i
Assignable Pin Name
P1, P2, P3, P4, or P5
P1, P2, P3, P4, or P5
P1, P2, P3, P4, or P5
P1, P2, P3, P4, or P5
P1, P2, P3, P4, or P5
P1, P2, P3, P4, or P5
P1, P2, or P3
P1, P2, or P3
Si5355
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