CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 49

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

DS646F2
7.12
7.12.1 Invert Signal Polarity (INV_AINX)
7.13
7.13.1 CLOCK ERROR (CLK ERROR)
7.13.2 ADC Overflow (ADCX_OVFL)
7.14
Reserved
Reserved
Reserved
7
7
7
ADC Channel Invert (Address 17h)
Status (Address 19h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
Status Mask (Address 1Ah)
Default = 0000
Function:
The bits of this register serve as a mask for the error sources found in the register
(Read Only)” on page
affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not
affect status register. The bit positions align with the corresponding bits in the Status register.
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active
during the error condition. See
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42438 ADC signal path of each of the
associated ADC’s.
Reserved
Reserved
Reserved
6
6
6
Reserved
Reserved
INV_AIN6
49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will
5
5
5
“System Clocking” on page 33
Reserved
Reserved
INV_AIN5
4
4
4
CLK Error_M
CLK Error
INV_AIN4
3
3
3
ADC3_OV
ADC3_OVFL
for valid clock ratios.
FL_M
INV_AIN3
2
2
2
ADC2_OVFL_M
ADC2_OVFL
INV_AIN2
1
1
“Status (Address 19h)
1
ADC1_OVFL_M
CS42438
ADC1_OVFL
INV_AIN1
0
0
0
49