CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 27

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

DS646F2
5.2
5.2.1
AIN6 Multiplexer
DAC Volume Control/Mute/Invert
ADC Volume Control
DAC Soft Ramp/Zero Cross
ADC Soft Ramp/Zero Cross
DAC Auto-Mute
Status Interrupt
Analog Inputs
5.2.1.1
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode. Single-ended oper-
ation is only supported for ADC3. See
5.2.1.2
Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.
Figure 9 on page 28
ended signals on all inputs, AIN1-AIN
filters.
For single-ended operation on ADC1-ADC
Control & DAC De-Emphasis (Address 05h)” on page 44
page 50
The gain/attenuation of the signal can be adjusted for each AINx independently through the
Control (Address 11h-16h)” on page
puts above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, re-
spectively, and cause the ADC Overflow bit in the register
to be set to a ‘1’.
Function
for required external components).
Hardware Mode
Software Mode
Table 2. Hardware Configurable Settings (Continued)
shows the full-scale analog input levels. The CS42438 also accommodates single-
Hardware Mode Feature Summary
AIN6B when ADC3 in Single-
Selects between AIN6A and
All DAC Volume = 0 dB, un-
Default Configuration
All ADC Volume = 0 dB
muted, not inverted
Immediate Change
Immediate Change
48. The ADC output data is in 2’s complement binary format. For in-
6
Section
Ended Mode
. See
Enabled
3
N/A
(AIN1 to AIN
“ADC Input Filter” on page 50
5.2.2.
“Status (Address 19h) (Read Only)” on page 49
6
), the ADCx_SINGLE bit in the register
must be set appropriately (see
Hardware Control
“AIN6_MUX” pin 2
-
-
-
-
-
-
for the recommended input
see
-
-
-
-
-
-
“AINX Volume
Section 5.2.2
CS42438
Figure 21 on
Note
“ADC
27