CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 29

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

DS646F2
5.2.3
5.2.4
5.2.5
5.2.5.1
The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode.
filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high.
5.2.5.2
The high-pass filter for ADC1/ADC2 can be enabled and disabled.
be independently enabled and disabled.
bit in the register
Hardware Mode
Single-Ended Mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup.
Analog input selection is then made via the AINx_MUX pins. See
Refer to
Software Mode
Single-Ended Mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the
AINx_MUX bits. See register
lections. Refer to
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the
corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-
sult. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS42438 with the high-pass filter enabled until the filter settles. See the Digital Filter
2. Disabling the high-pass filter and freezing the stored DC offset.
Characteristics for filter settling time.
Figure 10 on page 28
Hardware Mode
Software Mode
47 kΩ Pull-down
47 kΩ Pull-up
47 kΩ Pull-up
47 kΩ Pull-down
47 kΩ Pull-up
47 kΩ Pull-up
ADC_SDOUT
ADC_SDOUT
“ADC Control & DAC De-Emphasis (Address 05h)” on page
Figure 12 on page 32
Configuration Setting
(pin 13)
Configuration Setting
(pin 13)
Table 3. AIN5 Analog Input Selection
Table 4. AIN6 Analog Input Selection
“ADC Control & DAC De-Emphasis (Address 05h)” on page 44
for the internal ADC3 analog input topology.
AIN5_MUX
AIN6_MUX
(pin 1)
(pin 2)
High
High
Low
Low
X
X
for the internal ADC3 analog input topology.
The high-pass filters are controlled using the HPF_FREEZE
AIN5A Input (pin 50)
AIN5B Input (pin 49)
AIN5A Input (pin 52)
AIN5B Input (pin 51)
Differential Input (pins 50 & 49)
Differential Input (pins 52 & 51)
AIN5 Input Selection
AIN6 Input Selection
The high pass filter for ADC3 can
Tables 3-4
44.
for ADC3 set-up options.
The high pass
CS42438
for all bit se-
29