CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 33

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

DS646F2
5.4
5.4.1
5.4.2
5.5
5.5.1
System Clocking
The CODEC serial audio interface ports operate as a slave andaccept externally generated clocks.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be
an integer multiple of, and synchronous with, the system sample rate, Fs.
CODEC Digital Interface
The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with varying
bit depths from 16 to 32 as shown in . Data is clocked out of the ADC on the falling edge of SCLK and
clocked into the DAC on the rising edge.
TDM is the only interface supported in Hardware and Software Mode.
Hardware Mode
The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode.
The frequency of MCLK must be specified using the MFREQ (pin 3). See
cy range.
Software Mode
The frequency range of MCLK must be specified using the MFREQ bits in register
(MFREQ[2:0])” on page
TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring
after a an
but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling
edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the time slot.
Valid data lengths are 16, 18, 20, or 24.
SCLK must operate at 256Fs.
TDM
FS
MFREQ
rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted early,
0
1
1.5360 MHz to 12.8000 MHz
2.0480 MHz to 25.6000 MHz
43.
Table 5. MCLK Frequency Settings
Figure 13. De-Emphasis Curve
FS
Description
-10dB
Gain
0dB
dB
identifies the start of a new frame and is equal to the sample rate, Fs.
3.183 kHz
T1=50 µs
F1
SSM
10.61 kHz
256
512
F2
T2 = 15 µs
Ratio (xFs)
Frequency
DSM
N/A
256
Table 5
QSM
N/A
N/A
for the required frequen-
“MCLK Frequency
CS42438
33