CDB42438 Cirrus Logic Inc, CDB42438 Datasheet
CDB42438
Specifications of CDB42438
Related parts for CDB42438
CDB42438 Summary of contents
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... An auxiliary serial input is available for an additional two channels of PCM data. The CS42438 is available in a 52-pin MQFP package in Commercial (-10°C to +70°C) and Automotive (-40°C to +105°C) grades. The CDB42438 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please refer to Information” ...
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TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE ......................................................................................... 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. PIN DESCRIPTIONS - HARDWARE MODE 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 11 4. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13 RECOMMENDED OPERATING CONDITIONS ................................................................................... ...
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Recommended Power-Up Sequence ............................................................................................. 37 5.8.1 Hardware Mode ..................................................................................................................... 37 5.8.2 Software Mode ...................................................................................................................... 38 5.9 Reset and Power-Up ...................................................................................................................... 38 5.10 Power Supply, Grounding, and PCB Layout ................................................................................ 38 6. REGISTER QUICK REFERENCE ........................................................................................................ 39 7. REGISTER DESCRIPTION ...
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DAC Output Filter ........................................................................................................................... 53 9. ADC FILTER PLOTS ............................................................................................................................ 54 10. DAC FILTER PLOTS .......................................................................................................................... 56 11. PARAMETER DEFINITIONS .............................................................................................................. 58 12. REFERENCES .................................................................................................................................... 59 13. PACKAGE INFORMATION ................................................................................................................ 60 13.1 Thermal Characteristics ............................................................................................................... 60 14. ORDERING INFORMATION ...
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Figure 43.QSM Transition Band ................................................................................................................ 57 Figure 44.QSM Transition Band (detail) .................................................................................................... 57 Figure 45.QSM Passband Ripple .............................................................................................................. 57 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Configurable Settings ................................................................................................. 26 Table 3. AIN5 Analog ...
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PIN DESCRIPTIONS - SOFTWARE MODE SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN RST VLC DGND VLS SCLK MCLK ADC_SDOUT Pin Name # SCL/CCLK 1 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDOUT 2 Serial Control Data ...
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AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple- AUX_SDIN 17 ment serial audio data. AOUT1 +,- 20,19 AOUT2 ...
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Digital I/O Pin Characteristics Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Pin Name ...
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PIN DESCRIPTIONS - HARDWARE MODE AIN5_MUX AIN6_MUX MFREQ ADC3_HPF RST VLC FS VD DGND VLS SCLK MCLK ADC_SDOUT/ ADC3_SINGLE Pin Name # AIN5_MUX 1 Analog Input Multiplexer AIN6_MUX 2 ADC3. MFREQ 3 MCLK Frequency (Input) - Sets the required ...
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Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active AUX_LRCK 15 on the Auxiliary serial audio data line. AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial ...
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TYPICAL CONNECTION DIAGRAMS +3.3 V 0.01 µ µF 0.01 µF CS5341 A/D Converter +1.8 V Digital Audio to +5.0 V Processor Micro- Controller ** 2 kΩ 2 kΩ +1 0.1 µF ** Resistors ...
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V + 0.01 µF 10 µF 0.01 µF CS5341 A/D Converter +1 +5.0 V VLS Digital Audio Processor 0.1 µF * MUX configuration settings for AIN5-AIN6. See the ADC Input MUX section. Figure 2. Typical Connection Diagram ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Audio Interface Control Port Interface Ambient Temperature Commercial Automotive ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; ...
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ANALOG INPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): T Full-scale input sine wave: 1 kHz through the active input filter in Measurement Bandwidth kHz.) Parameter Fs=48 kHz, 96 kHz Dynamic Range A-weighted unweighted 40 ...
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ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): T Full-scale input sine wave: 1 kHz through the active input filter in Measurement Bandwidth kHz.) Parameter Fs=48 kHz, 96 kHz Dynamic Range A-weighted unweighted 40 ...
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ADC DIGITAL FILTER CHARACTERISTICS Parameter Single-Speed Mode (Note 10) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Double-Speed Mode (Note 10) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response ...
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ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): T Full-scale 997 Hz output sine wave (see ure 26 on page 54; Measurement Bandwidth kHz.) Parameter kHz, 96 kHz, 192 kHz Dynamic ...
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ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): T Full-scale 997 Hz output sine wave (see ment Bandwidth kHz.) Parameter kHz, 96 kHz, 192 kHz Dynamic Range 18 to 24-Bit A-weighted ...
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DAC1-4 3.3 µF + AOUTxx R L AGND Figure 3. Output Test Circuit for Maximum Load DS646F2 125 100 75 Analog Output 2 Figure 4. Maximum Loading CS42438 Safe Operating Region ...
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COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter Single-Speed Mode Passband (Frequency Response) Frequency Response kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 16) Double-Speed Mode Passband (Frequency Response) Frequency Response ...
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SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C Parameters Slave Mode RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate (FS pin) Double-Speed Mode SCLK Duty Cycle SCLK ...
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SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.) Parameters Master Mode Output Sample Rate (AUX_LRCK) AUX_SCLK Frequency AUX_SCLK Duty Cycle AUX_LRCK Edge to SCLK Rising Edge AUX_SDIN Setup Time Before SCLK Rising Edge AUX_SDIN ...
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SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (VLC = 1 5.0 V, VLS = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA C Parameter SCL Clock Frequency ...
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SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (VLC = 1 5.0 V, VLS = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT C Parameter CCLK Clock Frequency ...
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DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters Normal Operation (Note 25) Power Supply Current Power Dissipation VLS = VLC = Power Supply Rejection Ratio (Note ...
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APPLICATIONS 5.1 Overview The CS42438 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital con- verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC) also implemented using multi-bit delta-sigma techniques. Other functions ...
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Function AIN6 Multiplexer DAC Volume Control/Mute/Invert ADC Volume Control DAC Soft Ramp/Zero Cross ADC Soft Ramp/Zero Cross DAC Auto-Mute Status Interrupt Table 2. Hardware Configurable Settings (Continued) 5.2 Analog Inputs 5.2.1 Line-Level Inputs AINx+ and AINx- are the line-level differential ...
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V 2.5 V 1.1 V 3.9 V 2.5 V 1.1 V 5.2.2 ADC3 Analog Input ADC3 accommodates differential as well as single-ended inputs. In Single-Ended Mode, an internal MUX selects from up to four single-ended inputs. AIN5A AIN5B AIN5+/- ...
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Hardware Mode Single-Ended Mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup. Analog input selection is then made via the AINx_MUX pins. See Refer to Figure 10 on page 28 Configuration Setting ADC_SDOUT (pin 13) 47 ...
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Analog Outputs 5.3.1 Initialization The initialization and Power-Down sequence flow chart is shown in enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit ...
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No Power Aout bias = ? 3. No audio signal generated. Power-Down (Power Applied VA/2. 2. Aout = HI- audio signal generated. 4. Control Port Registers reset to default. RST ...
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V VA 5.3.3 Digital Volume Control 5.3.3.1 Hardware Mode DAC Volume Control and Mute are not accessible in Hardware Mode. 5.3.3.2 Software Mode Each DAC’s output level is controlled via the Volume Control registers operating over the range of ...
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System Clocking The CODEC serial audio interface ports operate as a slave andaccept externally generated clocks. The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be an integer multiple of, and synchronous ...
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FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample and must be held valid for at least 1 SCLK period. Note: The ADC does not meet the timing requirements ...
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Left-Justified AUX_LRCK AUX_SCLK AUX_SDIN AUX1 5.7 Control Port Description and Timing The control port is used to access the registers, in Software Mode, allowing the CS42438 to ...
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ADDRESS 1001111 R High Impedance MAP = Memory Address Pointer, 8 bits, MSB first Figure 17. Control Port Timing in SPI ...
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SCL CHIP ADDRESS (WRITE) SDA AD1 AD0 0 ACK START Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. ...
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... FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and power supply arrangements. ...
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REGISTER QUICK REFERENCE Software Mode register defaults are as shown. Note: The default value in all “Reserved” registers must be pre- served. Addr Function 7 01h ID Chip_ID3 Chip_ID2 p 41 default 0 02h Power Con- PDN_ADC3 PDN_ADC2 trol ...
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Addr Function 7 11h Vol. Control AIN1 AIN1 VOL7 p 47 default 0 12h Vol. Control AIN2 AIN2 VOL7 p 48 default 0 13h Vol. Control AIN3 AIN3 VOL7 p 47 default 0 14h Vol. Control AIN4 AIN4 VOL7 p ...
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REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit-definition tables for bit assignment information. The default state of each bit after a power- ...
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Power Control (Address 02h PDN_ADC3 PDN_ADC2 PDN_ADC1 7.3.1 Power Down ADC Pairs (PDN_ADCX) Default = Disable 1 - Enable Function: When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ...
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Functional Mode (Address 03h Reserved Reserved Reserved 7.4.1 MCLK Frequency (MFREQ[2:0]) Default = 000 Function: Sets the appropriate frequency for the supplied MCLK. For TDM operation, SCLK must equal 256Fs. MCLK can be equal to or greater ...
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ADC Control & DAC De-Emphasis (Address 05h ADC1-2_HPF ADC3_HPF DAC_DEM FREEZE FREEZE 7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC1 ...
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Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2 digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driv- ...
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The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on all channels is determined by the AOUT1 and AIN1 Volume Control register and the other ...
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Mute ADC Serial Port (MUTE ADC_SP) Default = Disabled 1 - Enabled Function: When enabled, the ADC Serial Port will be muted. 7.8 DAC Channel Mute (Address 07h AOUT6_MUTE AOUT8_MUTE AOUT7_MUTE 7.8.1 Independent Channel ...
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DAC Channel Invert (Address 10h INV_AOUT6 INV_AOUT8 INV_AOUT7 7.10.1 Invert Signal Polarity (INV_AOUTX) Default = Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels. 7.11 ...
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ADC Channel Invert (Address 17h Reserved Reserved INV_AIN6 7.12.1 Invert Signal Polarity (INV_AINX) Default = Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels. 7.13 ...
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EXTERNAL FILTERS 8.1 ADC Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which ...
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Passive Input Filter The passive filter implementation shown in will not provide optimum source impedance for the ADC modulators. Full analog performance will there- fore not be realized using a passive filter. In this topology the distortion performance is ...
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Passive Input Filter w/Attenuation Some applications may require signal attenuation prior to the ADC. The full-scale input voltage will scale with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is approximately 2.8 Vpp, ...
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DAC Output Filter The recommended active and passive output filters are shown below. DAC1-4 AOUTx - AOUTx + DAC1-4 AOUTx+ DS646F2 1800 pF 4.75 kΩ 390 pF C0G 5.49 kΩ 2.94 kΩ 887 Ω 1200 pF 1.65 ...
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ADC FILTER PLOTS Figure 26. SSM Stopband Rejection -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) Figure 28. SSM Transition Band (Detail) 0 -10 -20 ...
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Frequency (normalized to Fs) Figure 32. DSM Transition Band (Detail) DS646F2 0 . ...
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FILTER PLOTS Figure 34. SSM Stopband Rejection Figure 36. SSM Transition Band (detail) Figure 38. DSM Stopband Rejection 56 Figure 35. SSM Transition Band 0.05 0 -0.05 -0. 1 -0.15 -0. 2 -0.25 0 0.05 0.1 0.15 0.2 0.25 ...
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Figure 40. DSM Transition Band (detail) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) Figure 42. QSM Stopband Rejection 0 -5 -10 -15 -20 -25 -30 -35 ...
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DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with ...
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Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated ...
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INFORMATION 52L MQFP PACKAGE DRAWING D D1 DIM MIN A --- A1 0.000 B 0.009 D --- D1 --- E --- E1 --- e* --- L 0.029 ∝ 0.00° 13.1 Thermal Characteristics Parameter Junction to Ambient Thermal Impedance 60 ...
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... Product Description 6-in, 8-out, TDM CODEC CS42438 for Surround Sound Apps CDB42438 CS42438 Evaluation Board 15.REVISION HISTORY Revision Updated temperature and voltage specifications in F1 Added test conditions to the Analog Input and Analog Output Characteristics tables. Updated input impedance specification for Differential and Single-Ended Inputs in F2 tics (Commercial)” ...