EVAL-ADF4360-7EBZ1 Analog Devices Inc, EVAL-ADF4360-7EBZ1 Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADF4360-7EBZ1
• Description: PLL/Frequency Synthesizer EVAL BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4360-7EBZ1

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Integer-N Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: ADF4360-7
• Kit Contents: Board
• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4360-7
• Primary Attributes: Single Integer-N PLL with VCO
• Secondary Attributes: 900MHz, 200kHz PFD
• Frequency: 1.8GHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: EVAL-ADF4360-7EB1; EVAL-ADF4360-7EB1; Q5173330; Q5652985

MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 19 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When a lock has been detected, this output is high with narrow
low-going pulses.
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 19. MUXOUT Circuit
MUX
CONTROL
DGND
DV
DD
MUXOUT
Rev. A | Page 11 of 28
Table 5. C2 and C1 Truth Table
C2
0
0
1
1
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 20, to allow a wide frequency range to
be covered without a large VCO sensitivity (K
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is:
1.
2.
3.
During band select, which takes five PFD cycles, the VCO V
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8 and
is controlled by Bits BSC1 and BSC2 in the R counter latch. Where
the required PFD frequency exceeds 1 MHz, the divide ratio should
be set to allow enough time for correct band selection.
R counter latch
Control latch
N counter latch
Control Bits
3.0
2.5
2.0
1.5
1.0
0.5
450
C1
0
1
0
1
Figure 20. Frequency vs. V
500
FREQUENCY (MHz)
Data Latch
Control Latch
R Counter
N Counter (A and B)
Test Mode Latch
550
TUNE
, ADF4360-7
600
V
) and resultant
ADF4360-7
650
TUNE