AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet - Page 6

• Manufacturer Part Number: AD9122-M5372-EBZ
• Description: DAC Evaluation Board W/ ADL5372 Modulator
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9122-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9122
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9122, ADL5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9122
DIGITAL SPECIFICATIONS
T
otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
CMOS OUTPUT LOGIC LEVEL
LVDS RECEIVER INPUTS
DAC CLOCK INPUT (DACCLKP, DACCLKN)
REFCLK INPUT (REFCLKP, REFCLKN)
SERIAL PERIPHERAL INTERFACE
Setup Time, CS to SCLK (t
1
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK Cycles)
LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.
MIN
1× Interpolation (With or Without Modulation)
2× Interpolation (With or Without Modulation)
4× Interpolation (With or Without Modulation)
8× Interpolation (With or Without Modulation)
Inverse Sinc
Fine Modulation
Power-Up Time
Input V
Input V
Input V
Input V
Input V
Output V
Output V
Output V
Output V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK Frequency (PLL Mode)
REFCLK Frequency (SYNC Mode)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (t
Minimum Pulse Width Low (t
Setup Time, SDI to SCLK (t
Hold Time, SDI to SCLK (t
Data Valid, SDO to SCLK (t
to T
MAX
IN
IN
IN
IN
IN
Logic High
Logic High
Logic High
Logic Low
Logic Low
OUT
OUT
OUT
OUT
, AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
Logic High
Logic High
Logic High
Logic Low
1
DCSB
IA
or V
DH
DV
DS
)
)
)
)
IB
PWOL
PWH
IDTH
IDTHH
)
)
to V
IDTHL
IN
Conditions
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V, 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V, 2.5 V, 3.3 V
Applies to DATA, DCI, and FRAME Inputs
See Table 5
Self biased input, ac couple
1 GHz ≤ f
See Multichip Synchronization section for conditions
VCO
Rev. A | Page 6 of 60
≤ 2.1 GHz
OUTFS
Min
= 20 mA, maximum sample rate, unless
Typ
64
135
292
608
20
8
260
Min
1.2
1.6
2.0
1.4
1.8
2.4
825
−100
80
100
1200
100
15.625
0
40
1.9
0.2
2.3
Max
Typ
20
500
1.25
500
1.25
1.4
Max
0.6
0.8
0.4
1675
+100
120
2000
2000
600
600
12.5
12.5
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ms
Unit
V
V
V
V
V
V
V
V
V
mV
mV
mV
Ω
mV
V
MHz
mV
V
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns