AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet - Page 40

• Manufacturer Part Number: AD9122-M5372-EBZ
• Description: DAC Evaluation Board W/ ADL5372 Modulator
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9122-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9122
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9122, ADL5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9122
NCO MODULATION
The digital quadrature modulator makes use of a numerically
controlled oscillator, a phase shifter, and a complex modulator
to provide a means for modulating the signal by a programmable
carrier signal. A block diagram of the digital modulator is shown in
Figure 58. The fine modulation provided by the digital modulator,
in conjunction with the coarse modulation of the interpolation
filters and premodulation block, allows the signal to be placed
anywhere in the output spectrum with very fine frequency
resolution.
The quadrature modulator is used to mix the carrier signal
generated by the NCO with the I and Q signal. The NCO produces
a quadrature carrier signal to translate the input signal to a new
center frequency. A complex carrier signal is a pair of sinusoidal
waveforms of the same frequency, offset 90° from each other.
The frequency of the complex carrier signal is set via FTW[31:0]
in Register 0x30 through Register 0x33.
The NCO operating frequency, f
bypassed) or twice f
the complex carrier signal can be set from dc up to f
frequency tuning word (FTW) is calculated as
The generated quadrature carrier signal is mixed with the I and
Q data. The quadrature products are then summed into the I
and Q data paths, as shown in Figure 58.
Updating the Frequency Tuning Word
The frequency tuning word registers are not updated immediately
upon writing as other configuration registers do. After loading
the FTW registers with the desired values, Bit 0 of Register 0x36
must transition from 0 to 1 for the new FTW to take effect.
DATAPATH CONFIGURATION
Configuring the AD9122 datapath starts with the application
requirements of the input data rate, the interpolation ratio, the
output signal bandwidth, and the output signal center frequency.
FTW
=
f
CARRIER
f
NCO
DATA
×
2
(HB1 enabled). The frequency of
32
NCO
, is at either f
Q DATA
I DATA
NCO PHASE OFFSET
Figure 58. Digital Quadrature Modulator Block Diagram
INTERPOLATION
INTERPOLATION
DATA
FTW[31:0]
NCO
(HB1
[15:0]
INVERSION
SPECTRAL
. The
Rev. A | Page 40 of 60
–1
COSINE
NCO
SINE
0
1
Given these four parameters, the first step in configuring the
datapath is to verify that the device supports the bandwidth
requirements. The modes of the interpolation filters are then
chosen. Finally, any additional frequency offset requirements
are determined and applied with premodulation and NCO
modulation.
Determining Datapath Signal Bandwidth
The available signal bandwidth of the datapath is dependent on
the center frequency of the output signal in relation to the center
frequency of the interpolation filters used. Signal center frequencies
offset from the center frequencies of the half-band filters lower
the available signal bandwidth.
When correctly configured, the available complex signal band-
width for 2× interpolation is always 80% of the input data rate.
The available signal bandwidth for 4× interpolation vs. output
frequency varies between 50% and 80% of the input data rate,
as shown in Figure 59. Note that in 4× interpolation mode,
f
four times from dc to f
Configuring 4× interpolation using the HB2 and HB3 filters can
lower the power consumption of the device at the expense of
bandwidth. The lower curve in Figure 59 shows that the supported
bandwidth in this mode varies from 30% to 50% of f
DAC
Figure 59. Signal Bandwidth vs. Center Frequency of the Output Signal,
= 4 × f
0.8
0.5
0.3
–
DATA
+
HB1 AND HB2
; therefore, the data shown in Figure 59 repeats
0.2
OUT_I
OUT_Q
DAC
4× Interpolation
.
0.4
HB2 AND HB3
f
OUT
/
f
DATA
0.6
0.8
DATA
1.0
.