AD9122 Analog Devices, AD9122 Datasheet
AD9122
Specifications of AD9122
Available stocks
Related parts for AD9122
AD9122 Summary of contents
Page 1
... W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point GENERAL DESCRIPTION The AD9122 is a dual, 16-bit, high dynamic range digital-to- analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency. COMPLEX BASEBAND DC ...
Page 2
... Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Differences Between AD9122R1 and AD9122R2 ...................... 18 Device Marking of AD9122R1 and AD9122R2 ..................... 18 Theory of Operation ...................................................................... 19 Serial Port Operation ................................................................. 19 Data Format ................................................................................ 19 Serial Port Pin Descriptions ...................................................... 19 Serial Port Options ..................................................................... 20 Device Configuration Register Map and Descriptions ......... 21 LVDS Input Data Ports ...
Page 3
... Changes to Table 3 ............................................................................ 6 Changes to Table 5 ............................................................................ 7 Changes to Table 6 ............................................................................ 8 Changes to Figure 3 and Table 8 ..................................................... 9 Changes to Differences Between AD9122R1 and AD9122R2 Section and Device Marking of AD9122R1 and AD9122R2 Section .............................................................................................. 18 Changes to Figure 40 and Figure 41 ............................................. 20 Changes to Table 10 ........................................................................ 21 Changes to Table 11 ........................................................................ 23 Changes to LVDS Input Data Ports Section and Figure 45 ....... 32 Moved Interface Timing Section ................................................... 32 Moved Figure 46 and Table 13 ...
Page 4
... AD9122 FUNCTIONAL BLOCK DIAGRAM D15P/D15N f /2 DATA FIFO PRE HB1 MOD D0P/D0N DCI FRAME SERIAL PROGRAMMING INPUT/OUTPUT REGISTERS PORT NCO 10 AND HB2 HB3 MOD INTERNAL CLOCK TIMING AND CONTROL LOGIC POWER-ON MULTICHIP RESET SYNCHRONIZATION Figure 2. Rev Page 1.2G AUX DAC 1 ...
Page 5
... Guaranteed 20 0.04 100 30 1.2 5 3.13 3.3 1.71 1.8 1.71 1.8 1.71 1.8/3.3 834 913 1135 55 85 444 6.5 260 −40 +25 Rev Page AD9122 Max Unit Bits LSB LSB +0.001 % FSR +3.6 % FSR 31.66 mA +1.0 V +0.3 % FSR/V MΩ ns ppm/°C ppm/°C ppm/°C V kΩ 3.47 V 1.89 V 1. 1241 ...
Page 6
... AD9122 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN Input V Logic Low IN CMOS OUTPUT LOGIC LEVEL Output V Logic High OUT Output V Logic Low OUT 1 LVDS RECEIVER INPUTS Input Voltage Range, V ...
Page 7
... Rev Page AD9122 Typ Max Unit 78 dBc 80 dBc 69 dBc 72 dBc 84 dBc 86 dBc 84 dBc 81 dBc −162 dBm/Hz −163 dBm/Hz − ...
Page 8
... AD9122 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating AVDD33 to AVSS, EPAD, CVSS, DVSS −0 +3.6 V IOVDD to AVSS, EPAD, CVSS, DVSS −0 +3.6 V DVDD18, CVDD18 to AVSS, EPAD, −0 +2.1 V CVSS, DVSS AVSS to EPAD, CVSS, DVSS −0 +0.3 V EPAD to AVSS, CVSS, DVSS −0 +0.3 V CVSS to AVSS, EPAD, DVSS − ...
Page 9
... IRQ 7 AD9122 D15P 8 D15N 9 TOP VIEW NC 10 (Not to Scale) IOVDD 11 12 D14P 13 D14N 14 D13P 15 D13N 16 D12P 17 D12N 18 Figure 3. Pin Configuration Rev Page AD9122 54 RESET SCLK 51 SDIO 50 SDO 49 DVDD18 48 D0N D0P 47 46 D1N 45 D1P 44 DVSS 43 DVDD18 42 D2N 41 D2P 40 D3N ...
Page 10
... AD9122 Pin No. Mnemonic Description 25 D8P Data Bit 8, Positive. 26 D8N Data Bit 8, Negative. 27 DCIP Data Clock Input, Positive. 28 DCIN Data Clock Input, Negative. 29 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 30 DVSS Digital Common. 31 D7P Data Bit 7, Positive. 32 D7N Data Bit 7, Negative ...
Page 11
... THIRD HARMONIC FS –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 f (MHz) OUT Figure 9. Harmonics vs. f over I , 2× Interpolation, OUT 400 MSPS, Digital Scale = 0 dBFS DATA AD9122 350 400 450 350 400 450 350 400 450 ...
Page 12
... AD9122 – 250MSPS DATA f = 400MSPS –70 DATA –71 –72 –73 –74 –75 –76 –77 –78 – 100 150 200 250 f (MHz) OUT Figure 10. Highest Digital Spur vs. f over f OUT Digital Scale = 0 dBFS –60 –65 –70 –75 –80 – ...
Page 13
... Figure 20. IMD vs. f over I , 2× Interpolation, OUT 400 MSPS, Digital Scale = 0 dBFS DATA PLL ON PLL OFF 50 100 150 200 250 300 350 400 f (MHz) OUT , 4× Interpolation 200 MSPS, OUT DATA = 20 mA, PLL On and PLL Off FS AD9122 450 450 450 ...
Page 14
... AD9122 –152 f 1×, = 200MSPS DATA f 2×, = 200MSPS DATA –154 f 4×, = 200MSPS DATA f 8×, = 100MSPS DATA –156 –158 –160 –162 –164 –166 0 50 100 150 200 250 f (MHz) OUT Figure 22. One-Tone NSD vs. f over Interpolation, OUT Digital Scale = 0 dBFS, I ...
Page 15
... First Alternate Channel, PLL On and PLL Off INTERPOLATION FACTOR = 2×, PLL OFF INTERPOLATION FACTOR = 4×, PLL OFF INTERPOLATION FACTOR = 2×, PLL ON INTERPOLATION FACTOR = 4×, PLL ON 100 200 300 400 f (MHz) OUT over Interpolation, OUT Second Alternate Channel, PLL On and PLL Off AD9122 500 500 500 ...
Page 16
... AD9122 START 133.06MHz VBW 30kHz #RES BW 30kHz SWEEP 143.6ms (601 PTS) RMS RESULTS FREQ LOWER OFFSET REF BW dBc dBm CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96 –10.00dBm/ 10.00MHz 3.840MHz –85.33 –95.33 3.840MHz 15.00MHz 2.888MHz –95.81 –95.81 Figure 34. One-Carrier W-CDMA ACLR Performance ~150 MHz STOP 166 ...
Page 17
... By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev Page AD9122 /2. Images that typically DATA (output data rate) can be greatly suppressed. DAC ...
Page 18
... IOVDD supply voltage range. For the AD9122R1, the valid operational voltage range for IOVDD is 1 2.5 V ± 10%. For the AD9122R2, the valid operational voltage range for IOVDD is 1 3.3 V ± 10%. • Reduction in spurs level variation. ...
Page 19
... THEORY OF OPERATION The AD9122 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single side- band (SSB) transmitters. The speed and performance of the AD9122 allow wider bandwidths and more carriers to be syn- thesized than in previously available DACs ...
Page 20
... AD9122 SERIAL PORT OPTIONS The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB_FIRST bit (Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0). When LSB_FIRST = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte ...
Page 21
... DCI Delay[1:0] FIFO Phase Offset[2:0] FIFO soft FIFO soft align ack align request Bypass Select Send phase sideband I data to comp and Q data dc offset AD9122 Default 0x00 0x10 0x00 0x00 0x00 N/A N/A 0x3F 0x40 0xD1 0xD9 N/A N/A 0x48 0x00 N/A N/A ...
Page 22
... AD9122 Addr (Hex) Register Name Bit 7 0x1C HB1 control 0x1D HB2 control 0x1E HB3 control 0x1F Chip ID 0x30 FTW LSB 0x31 FTW 0x32 FTW 0x33 FTW MSB 0x34 NCO phase offset LSB 0x35 NCO phase offset MSB 0x36 NCO FTW update ...
Page 23
... PLL lock lost enable interrupt for PLL locked enable interrupt for sync signal lost enable interrupt for sync signal locked enable interrupt for FIFO Warning enable interrupt for FIFO Warning 2. Rev Page AD9122 Bit 2 Bit 1 Bit Default ...
Page 24
... AD9122 Register Address Name (Hex) Bits Name Interrupt 0x05 [7:5] Set to 0 Enable 4 Enable AED compare pass 3 Enable AED compare fail 2 Enable SED compare fail [1:0] Set to 0 Event Flag 0x06 7 PLL lock lost 6 PLL locked 5 Sync signal lost 4 Sync signal locked 1 FIFO Warning 1 ...
Page 25
... The offset unit is in DACCLK cycles. This register enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. … 111111 = 63 DACCLK cycles. Rev Page AD9122 Default N/A N/A N/A ...
Page 26
... AD9122 Register Address Name (Hex) Bits Name Sync Status 0x12 7 Sync lost 6 Sync locked 0x13 [7:0] Sync Phase Readback[7:0] Data 0x15 5 LVDS FRAME level high Receiver 4 LVDS FRAME level low Status 3 LVDS DCI level high 2 LVDS DCI level low 1 LVDS data level high ...
Page 27
... Rev Page filter pass band is from IN1 ; filter pass band is from IN1 . IN2 . ; filter pass band is IN2 . ; filter pass band is IN2 ; filter pass band is IN2 . ; filter pass band is IN2 AD9122 Default 000000 0 ...
Page 28
... IN3 from 1. IN3 1 = bypass the third-stage interpolation filter. This register identifies the device as an AD9122. See Register 0x33. See Register 0x33. See Register 0x33. FTW[31:0] is the 32-bit frequency tuning word that deter- mines the frequency of the complex carrier generated by the on-chip NCO ...
Page 29
... Q DAC into sleep mode (fast wake-up mode). Q DAC FS Adj[9:0] sets the full-scale current of the Q DAC. The full-scale current can be adjusted from 8. 31. step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. See Register 0x47, Bits[1:0]. Rev Page AD9122 Default 00000000 00000000 11111001 0 01 00000000 ...
Page 30
... AD9122 Register Address Name (Hex) Bits Name Q Aux DAC 0x47 7 Q aux DAC sign Control 6 Q aux DAC current direction 5 Q aux DAC sleep [1:0] Q Aux DAC[9:8] Die Temp 0x48 [6:4] FS Current[2:0] Range Control [3:1] Reference Current[2:0] 0 Capacitor value Die Temp 0x49 [7:0] Die Temp[7:0] ...
Page 31
... Errors Detected I_BITS[15:0] indicates which bits were received in error. See Register 0x73. Errors Detected Q_BITS[15:0] indicates which bits were received in error. This value corresponds to the die revision number. 0001 = Die Revision 1. 0011 = Die Revision 2. Rev Page AD9122 Default 11000110 10101010 00000000 00000000 00000000 00000000 N/A ...
Page 32
... AD9122 LVDS INPUT DATA PORTS The AD9122 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in word, byte, and nibble formats. In word, byte, and nibble modes, the data is sent over 16-bit, 8-bit, and 4-bit LVDS data buses, respectively ...
Page 33
... DCI FRAME FIFO SOFT ALIGN REQUEST REG 0x18[1] FIFO OPERATION The AD9122 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data t arriving at the DAC input ports and the internal DAC data rate DATA clock. The FIFO acts as a buffer that absorbs timing variations ...
Page 34
... AD9122 Resetting the FIFO When the AD9122 is powered on, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay important to reset the FIFO pointers to known states. The FIFO pointers can be initial- ized in two ways: via a write sequence to the serial port or by strobing the FRAME input ...
Page 35
... The synchronization signal is sampled by the DAC clock in the AD9122. The edge of the DAC clock used to sample the synchronization signal is selected by Bit 3 of Register 0x10. The FRAME signal is used to reset the FIFO write pointer. In ...
Page 36
... AD9122 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band (HB) interpolation filters, a quadrature modulator with a fine resolution NCO, phase and offset adjust- ment blocks, and an inverse sinc filter. PREMOD HB1 ...
Page 37
... MODE 2 0 –20 –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 f FREQUENCY (× ) (Hz) IN2 Figure 53. HB2, Even Filter Modes MODE 1 MODE 5 MODE 3 0 –20 –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 f FREQUENCY (× ) (Hz) IN2 Figure 54. HB2, Odd Filter Modes AD9122 MODE 6 1.6 1 MODE 7 1.6 1 IN2 ...
Page 38
... AD9122 Table 17 summarizes the HB2 and HB3 modes. Table 17. HB2 and HB3 Filter Modes Mode f f Input Data CENTER MOD 0 DC None Real or complex None Complex None Complex None Complex Real or complex ...
Page 39
... FTW registers with the desired values, Bit 0 of Register 0x36 must transition from for the new FTW to take effect. DATAPATH CONFIGURATION Configuring the AD9122 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. ...
Page 40
... AD9122 The available signal bandwidth for 8× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 59. Note that in 8× interpolation mode × therefore, the data shown in Figure 59 repeats DAC DATA eight times from DAC HB1, HB2, AND HB3 0 ...
Page 41
... The desired 140 MHz of bandwidth is 56 Figure 58, the value at 0.7 × this case, DATA 0.8 − 2(0.7 − 0.6) = 0.6. This verifies that the AD9122 supports a bandwidth of 60 The signal center frequency is 0.7 × f input signal is at baseband, the frequency shift required is also 0.7 × f ...
Page 42
... AD9122 DATA RATES vs. INTERPOLATION MODES Table 22 summarizes the maximum bus speed (f input data rates, and signal bandwidths with the various combi- nations of bus width modes and interpolation rates. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filters (HB1, HB2, or HB3) selected ...
Page 43
... Figure 61. DAC Output Currents vs. DAC Offset Value −1 ) filter is a nine-tap FIR filter. The composite −1 filter and the sin(x)/x response of the DAC 0.1 0.2 0.3 0 OUT DAC −1 Filter with sin(x)/x Roll-Off filter is disabled by default. It can be enabled by −1 bit to 0 (Register 0x1B, Bit 6). AD9122 0xFFFF . To DACCLK 0 .5 ...
Page 44
... AD9122 DAC INPUT CLOCK CONFIGURATIONS The AD9122 DAC sampling clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying uses the on-chip phase-locked loop (PLL), which accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies ...
Page 45
... Rev Page AD9122 Indication Move to higher VCO band VCO is operating in the higher end of the frequency band VCO is operating within an optimal region of the frequency band VCO is operating in the lower end of the frequency band ...
Page 46
... DACCODE for the DAC outputs are expressed where DACCODE = Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9122 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly ⎞ ⎞ ...
Page 47
... Figure 71. IMD vs. Output Common-Mode Voltage (f V OUT AUXILIARY DAC OPERATION The AD9122 has two auxiliary DACs: one associated with the I path and one associated with the Q path. These auxiliary DACs , is calculated as can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the positive (P) or negative (N) output of the associated transmit DAC ...
Page 48
... RBQP 50Ω 58 IOUT2P Figure 73. Typical Interface Circuitry Between the AD9122 and the ADL537x Family of Modulators The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC (one-half the full-scale current). Therefore, a single 50 Ω ...
Page 49
... Good sideband suppression requires both gain and phase matching of the I and Q signals. The I/Q phase adjust registers (Register 0x38 through Register 0x3B) and the DAC FS adjust registers (Register 0x40 and Register 0x44) can be used to calibrate the I and Q transmit paths to optimize sideband suppression. Rev Page AD9122 ...
Page 50
... PLL. The power dissipation of the PLL is typically 80 mW when enabled. Figure 76 through Figure 80 show the power dissipation of the AD9122 under a variety of operating conditions. All of the graphs were taken with data being supplied to both the I and Q DACs. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or the analog output frequency ...
Page 51
... Figure 80. DVDD18 Power Dissipation vs. f DATA TEMPERATURE SENSOR The AD9122 has a band gap temperature sensor for monitoring the temperature change of the AD9122. The temperature must be calibrated against a known temperature to remove the part- to-part variation on the band gap circuit used to sense the temperature ...
Page 52
... PLL of each device is phase locked to it. The following procedure must be carried out on each individual device. Procedure for Synchronization When Using the PLL In the initialization of the AD9122, all the clock signals (DACCLK, DCI, FRAME, synchronization, and REFCLK) must be present and stable before the synchronization feature is turned on. Configure the AD9122 for data rate, periodic synchronization by writing 0xC8 to the sync control register (Register 0x10) ...
Page 53
... Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock Configure the AD9122 for data rate, periodic synchronization by writing 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). ...
Page 54
... Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock Configure the AD9122 for FIFO rate, periodic synchronization by writing 0x88 to the sync control register (Register 0x10). Addi- tional synchronization options are available (see the Additional Synchronization Features section). ...
Page 55
... AN-1093 Application Note, “Synchronization of Multiple AD9122 TxDAC+ Converters. ” Sync Status Bits When the sync locked bit (Register 0x12, Bit 6) is set, it indicates that the synchronization logic has reached alignment. This align- ment is determined when the clock generation state machine phase is constant. Alignment takes from (11 + averaging) × ...
Page 56
... AD9122 INTERRUPT REQUEST OPERATION The AD9122 provides an interrupt request output signal on Pin 7 ( IRQ ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device ...
Page 57
... INTERFACE TIMING VALIDATION The AD9122 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED circuitry compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port ...
Page 58
... AD9122 SED EXAMPLE Normal Operation The following example illustrates the SED configuration for continuously monitoring the input data and assertion of the IRQ pin when a single error is detected. 1. Load the following comparison values. (Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test ...
Page 59
... EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9122, certain sequences should be followed. This section shows an example start-up routine. This example uses the configuration described in the Device Configuration section. DEVICE CONFIGURATION The following device configuration is used for this example: • 122.88 MSPS DATA • ...
Page 60
... PLANE ORDERING GUIDE 1 Model Temperature Range AD9122BCPZ −40°C to +85°C AD9122BCPZRL −40°C to +85°C AD9122-M5372-EBZ AD9122-M5375-EBZ RoHS Compliant Part. ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 0.42 0.24 0.50 9.75 BSC BSC SQ 0 ...