AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet
AD9122-M5372-EBZ
Specifications of AD9122-M5372-EBZ
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AD9122-M5372-EBZ Summary of contents
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... ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8 31.7 mA. The AD9122 comes in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. ...
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... Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Differences Between the AD9122R1 and AD9122R2 ............... 18 Theory of Operation ...................................................................... 19 Serial Port Operation ................................................................. 19 Data Format ................................................................................ 19 Serial Port Pin Descriptions ...................................................... 19 Serial Port Options ..................................................................... 20 Device Configuration Register Map and Descriptions ......... 21 LVDS Input Data Ports ...
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... Changes to Table 2 ............................................................................ 6 Changes to Table 5 ............................................................................ 7 Change to IOVDD Rating in Table 6 .............................................. 8 Changes to Table 8 ............................................................................ 9 Changes to Figure 10 to Figure 15 ................................................ 12 Added Differences Between the AD9122R1 and AD9122R2 Section, Added Figure 36 and Figure 37; Renumbered Sequentially ...................................................................................... 18 Changes to Table 10 ........................................................................ 21 Changes to Table 11 ........................................................................ 23 Changes to FIFO Operation Section ............................................ 33 Changes to Resettling the FIFO Section and Replaced Table 13 ...
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... SERIAL PROGRAMMING INPUT/OUTPUT REGISTERS PORT 16 I OFFSET NCO 10 AND HB2 HB3 Q OFFSET MOD 16 SYNC POWER-ON MULTICHIP RESET SYNCHRONIZATION Figure 2. AD9122 Functional Block Diagram Rev Page 1.2G AUX DAC 1 16-BIT INV DAC CLK SINC 16 1.2G AUX DAC 1 16-BIT REF 10 10 AND BIAS ...
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... Rev Page AD9122 Max Unit Bits LSB LSB +0.001 % FSR +3.6 % FSR 31.66 mA +1.0 V MΩ ppm/°C ppm/°C ppm/°C V kΩ ...
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... AD9122 DIGITAL SPECIFICATIONS AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN Input V Logic High IN Input V Logic High IN Input V Logic Low IN Input V Logic Low IN CMOS OUTPUT LOGIC LEVEL Output V Logic High ...
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... Rev Page AD9122 Typ Max Unit 78 dBc 80 dBc 69 dBc 72 dBc 84 dBc 86 dBc 84 dBc 81 dBc −162 dBm/Hz −163 dBm/Hz − ...
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... AD9122 ABSOLUTE MAXIMUM RATINGS Table 6. With Parameter Respect To AVDD33 AVSS, EPAD, CVSS, DVSS IOVDD AVSS, EPAD, CVSS, DVSS DVDD18, CVDD18 AVSS, EPAD, CVSS, DVSS AVSS EPAD, CVSS, DVSS EPAD AVSS, CVSS, DVSS CVSS AVSS, EPAD, DVSS DVSS AVSS, EPAD, CVSS FSADJ, REFIO, ...
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... FRAMEP 5 FRAMEN 6 IRQ 7 AD9122 D15P 8 D15N 9 TOP VIEW NC 10 (Not to Scale) IOVDD 11 DVDD18 12 D14P 13 D14N 14 D13P 15 D13N 16 D12P 17 D12N 18 Figure 3. Pin Configuration Rev Page AD9122 54 RESET SCLK 51 SDIO 50 SDO 49 DVDD18 48 D0N 47 D0P 46 D1N 45 D1P 44 DVSS 43 DVDD18 42 D2N 41 D2P 40 D3N 39 D3P 38 D4N ...
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... AD9122 Pin No. Mnemonic Description 26 D8N Data Bit 8, Negative. 27 DCIP Data Clock Input, Positive. 28 DCIN Data Clock Input, Negative. 29 DVDD18 1.8 V Digital Supply. 30 DVSS Digital Common. 31 D7P Data Bit 7, Positive. 32 D7N Data Bit 7, Negative. 33 D6P Data Bit 6, Positive. 34 D6N Data Bit 6, Negative. ...
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... THIRD HARMONIC –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 f (MHz) OUT over f , 2× Interpolation, Figure 9. Second Harmonic vs. f OUT 400 MSPS, Digital Scale = 0 dBFS DATA AD9122 350 400 450 350 400 450 350 400 450 ...
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... AD9122 – 250MSPS DATA f = 400MSPS –70 DATA –71 –72 –73 –74 –75 –76 –77 –78 – 100 150 200 250 f (MHz) OUT Figure 10. Highest Digital Spur vs. f over f OUT Digital Scale = 0 dBFS –60 –65 –70 –75 –80 – 100 150 200 ...
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... Figure 20. IMD vs. f –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 350 400 450 0 Figure 21. IMD vs. f Rev Page AD9122 0dBFS –6dBFS –12dBFS –18dBFS 50 100 150 200 250 300 350 400 f (MHz) OUT over Digital Scale, 2× Interpolation, OUT f ...
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... AD9122 –152 f 1×, = 200MSPS DATA f 2×, = 200MSPS DATA –154 f 4×, = 200MSPS DATA f 8×, = 100MSPS DATA –156 –158 –160 –162 –164 –166 0 50 100 150 200 250 f (MHz) OUT Figure 22. 1-Tone NSD vs. f over Interpolation Rate, Digital Scale = 0 dBFS, ...
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... Figure 33. 1-Carrier W-CDMA ACLR vs. f DAC Rev Page AD9122 INTERPOLATION FACTOR = 2×, PLL OFF INTERPOLATION FACTOR = 4×, PLL OFF INTERPOLATION FACTOR = 2×, PLL ON INTERPOLATION FACTOR = 4×, PLL ON 100 200 300 400 f (MHz) OUT , Adjacent Channel, OUT PLL On vs ...
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... AD9122 START 133.06MHz VBW 30kHz #RES BW 30kHz SWEEP 143.6ms (601 PTS) RMS RESULTS FREQ LOWER OFFSET REF BW dBc dBm CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96 –10.00dBm/ 10.00MHz 3.840MHz –85.33 –95.33 3.840MHz 15.00MHz 2.888MHz –95.81 –95.81 Figure 34. 4-Carrier W-CDMA ACLR Performance ~150 MHz STOP 166 ...
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... By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev Page AD9122 /2. Images that typically DATA (output data rate) can be greatly suppressed. DAC ...
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... IOVDD supply voltage range. For the AD9122R1, the valid operational range for IOVDD is 1 2.5 V ± 10%. For the AD9122R2, the valid operational voltage range is 1 3.3 V ± 10%. • Reduction in spurs level variation. The AD9122R1 has a variation of the f between device startups ...
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... THEORY OF OPERATION The AD9122 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9122 allows wider bandwidths and more carriers to be synthesized than in previously available DACs ...
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... AD9122 SERIAL PORT OPTIONS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by LSB_FIRST (Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0). When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte ...
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... Sync Phase Readback[7:0] (6.2 format) LVDS LVDS LVDS LVDS FRAME FRAME DCI level DCI level high level low high level low Rev Page AD9122 Bit 1 Bit 0 Default 0x00 PLL lock 0x10 status Data bus width[1:0] 0x00 Enable Enable 0x00 FIFO FIFO ...
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... AD9122 Addr Reg Name (Hex) Bit 7 FIFO Status 0x18 FIFO FIFO Warning 1 Warning 2 FIFO Status 0x19 Datapath 0x1B Bypass Bypass Control premod Sinc HB1 Control 0x1C HB2 Control 0x1D HB3 Control 0x1E Chip ID 0x1F FTW LSB 0x30 FTW 0x31 FTW 0x32 ...
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... The device is held in reset when this bit written high and is held there until the bit is written low power down DAC power down DAC power down the input data receiver power down auxiliary ADC for temperature sensor PLL is locked. Rev Page AD9122 Bit 1 Bit 0 Default N/A Compare Compare 0x00 ...
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... AD9122 Reg Addr Name (Hex) Bit Name Data 03 7 Binary data format Format 6 Q data first 5 MSB swap 1:0 Data bus width Interrupt 04 7 Enable PLL lock lost Enable 6 Enable PLL locked 5 Enable sync signal lost 4 Enable sync signal locked 3 Enable sync phase ...
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... Selects the VCO band to be used. This bit is only active for Version 1 devices. For version 2 devices, this bit is inactive disables the PLL VCO enables the PLL VCO. Set this bit high prior to enabling PLL. Rev Page AD9122 Default ...
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... AD9122 Reg Addr Name (Hex) Bit Name PLL 0C 7:6 PLL Loop Control Bandwidth[1:0] 4:0 PLL Charge Pump Current[4:0] PLL 0D 7:6 N2[1:0] Control 4 PLL cross control enable 3:2 N0[1:0] 1:0 N1[1:0] PLL 0E 7 PLL lock Status 3:0 VCO Control Voltage[3:0] PLL 0F 5:0 ...
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... FIFO read and write pointers within ±2. FIFO read and write pointers are aligned after serial port initiated FIFO reset. Request FIFO read and write pointers alignment via serial port. FIFO read and write pointers aligned after hardware reset. Rev Page AD9122 Default ...
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... AD9122 Reg Addr Name (Hex) Bit Name FIFO 7:0 FIFO Level[7:0] 19 Status Datapath 1B 7 Bypass Premod Control 6 Bypass Sinc 5 Bypass NCO 3 NCO gain 2 Bypass phase compensation and dc offset 1 Select sideband 0 Send I data to Q data 1C 2:1 HB1[1:0] HB1 Control 0 Bypass HB1 HB2 ...
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... IN3 1 = bypasses third stage interpolation filter. This register identifies the device as an AD9122. See Register 0x33. See Register 0x33. See Register 0x33. FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO ...
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... AD9122 Reg Addr Name (Hex) Bit Name I DAC 3C 7:0 I DAC Offset[7:0] Offset LSB 3D 7:0 I DAC Offset[15:8] I DAC Offset MSB Q DAC 3E 7:0 Q DAC Offset[7:0] Offset LSB Q DAC 3F 7:0 Q DAC Offset[15:8] Offset MSB I DAC 40 7:0 I DAC FS Adj[7:0] FS Adjust I DAC DAC sleep Control 1:0 ...
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... Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. See Register 0x68. Compare Value Q0[15:0] is the word that is compared with the Q0 input sample captured at the input interface. Rev Page AD9122 Default ...
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... AD9122 Reg Addr Name (Hex) Bit Name Compare 6B 7:0 Compare Value Q0[15:8] Q0 MSBs Compare 6C 7:0 Compare Value I1[7:0] I1 LSBs Compare 6D 7:0 Compare Value I1[15:8] I1 MSBs Compare 6E 7:0 Compare Value Q1[7:0] Q1 LSBs Compare 6F 7:0 Compare Value Q1[15:8] Q1 MSBs SED I 70 7:0 Errors Detected ...
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... LVDS INPUT DATA PORTS The AD9122 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in word, byte, and nibble formats. In word, byte, and nibble modes, the data is sent over 16-bit, 8-bit, and 4-bit LVDS data busses, respectively. ...
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... FIFO depth should be maintained near half full (a difference of four between the write pointer and read pointer values). The FIFO depth represents the FIFO pipeline delay and is part of the overall latency of the AD9122. Resetting the FIFO To avoid a concurrent read and write to the same FIFO address and assure a fixed pipeline delay important to reset the FIFO pointers to known states ...
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... DATA DATA SAMPLING SAMPLING INTERVAL INTERVAL Figure 49. Timing Diagram for Input Data Ports Minimum Minimum Hold Setup Time (t ) Time ( −0.05 0.65 −0.23 0.95 −0.38 1.22 −0.47 1.38 AD9122 Sampling Interval ns 0.6 0.72 0.84 0.91 ...
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... AD9122 t DATA DACCLK/ REFCLK SAMPLING INTERVAL DCI t SDCI t HDCI Figure 50. Timing Diagram for Input Data Port (Data Rate Mode) Table 15. DCI to DACCLK Setup and Hold Times vs. DCI Delay Value DCI_DELAY Minimum Setup Register 0x16, Time (t SDCI Bits[1: −0.07 01 −0.24 10 −0.39 11 −0.49 Rev ...
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... IN1 Figure 52. HB1 Filter Modes ) of the filter. Mode 0 and IN1 . When operating in Mode 0 IN1 f f Input Data CENTER MOD DC None Real or complex f /2 None Complex Real or complex Complex IN IN AD9122 1.8 2.0 ...
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... AD9122 Figure 53 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 17 shows the pass-band flatness and stop-band rejection the HB1 filter supports at different bandwidths ...
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... Table 20. HB3 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% 0.24 0.28 0.32 40.8 42.4 45.6 49.8 55.6 Stop-Band Rejection (dB Rev Page 0.04 0.08 0.12 0.16 0.20 f (× ) IN3 Figure 57. Pass-Band Detail of HB3 Pass-Band Stop-Band ) Flatness (dB) Rejection (dB) IN3 0.001 85 0.0014 80 0.002 70 0.0093 60 0.03 50 0.1 40 AD9122 0.24 0.28 ...
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... FTW registers with the desired values, Bit 0 of Register 0x36 must transition from for the new FTW to take effect. DATAPATH CONFIGURATION Configuring the AD9122 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. ...
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... Bypass 001001 Bypass 010010 Bypass 011011 Bypass 100100 Bypass 101101 Bypass 110110 Bypass 111111 Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Rev Page AD9122 f Modulation f Shift SIGNAL CENTER DATA f f DATA DATA DATA DATA 2f 2f DATA ...
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... CENTER The desired 140 MHz of bandwidth is 56 Figure 59, the value at 0.7 × this case, 0.8 − 2(0.7 − 0.6) = 0.6. This verifies that the AD9122 supports DATA a bandwidth of 60 The signal center frequency is 0.7 × f input signal is at baseband, the frequency shift required is also 0.7 × ...
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... r(Q − I), −I, −r(Q + I), −Q, r(−Q + I),I, r(Q + I), … mode. This means S /2 mode. All other modulation modes require S f 150 300 300 600 600 1200 300 600 600 1200 1200 1200 600 800 1200 1200 1200 1200 AD9122 (MHz) DAC ...
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... AD9122 QUADRATURE PHASE CORRECTION The purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase adjust value can optimize image rejection in single sideband radios. Ordinarily, the I and Q channels have an angle of precisely 90° ...
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... DAC INPUT CLOCK CONFIGURATIONS DAC INPUT CLOCK CONFIGURATIONS The AD9122 DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip phased-locked loop (PLL) that accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies ...
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... AD9122 PLL Settings There are three settings for the PLL circuitry that should be programmed to their nominal values. The PLL values shown in Table 24 are the recommended settings for these parameters. Table 24. PLL Settings Address PLL SPI Control Register PLL Loop Bandwidth[1:0] 0x0C ...
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... DACCODE for the DAC outputs are expressed where DACCODE = Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9122 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or ⎞ ⎞ ...
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... Figure 72. IMD vs. Output Common-Mode Voltage (f AUXILIARY DAC OPERATION The AD9122 have two auxiliary DACs, one associated with the I path and one associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the output of the associated transmit DAC ...
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... RBQP 100Ω 50Ω 58 IOUT2P Figure 74. Typical Interface Circuitry Between the AD9122 and the ADL537x Family of Modulators BASEBAND FILTER IMPLEMENTATION Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal-level setting resistor across the modulator input ...
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... AD9122 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. This can be done using the ...
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... PLL is typically 80 mA when enabled. Figure 77 through Figure 81 detail the power dissipation of the AD9122 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or analog output frequency ...
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... DATA Figure 81. DVDD18 Power Dissipation vs. f TEMPERATURE SENSOR The AD9122 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed through Register 0x49 and Register 0x4A. The temperature of the die can be calculated by T where T accuracy is ±5 Estimates of the ambient temperature can be made if the power dissipation of the device is known ...
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... FIFO and a particular clock edge of the system clock. The AD9122 has provisions for enabling multiple devices to be synchronized to each other system clock. The AD9122 supports synchronization in two different modes, data rate mode and FIFO rate mode ...
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... AD9122 REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) SAMPLE RATE CLOCK SYNC CLOCK FPGA Figure 84. Typical Circuit Diagram for Synchronizing Devices to a System Clock To maintain synchronization, the skew between the REFCLK signals of the devices must be less than t SKEW also a setup-and-hold time to be observed between the DCI and data of each device and the REFCLK signal ...
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... These features are detailed in the Sync Status Bits and Timing Optimization sections that follow. Rev Page SKEW t t SU_SYNC H_SYNC 2× Interpolation = ½ × The REFCLK input is DCI CLK × SYNC_I DATA AD9122 + t SKEW OUTDLY ...
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... AD9122 Sync Status Bits When the sync locked bit (Register 0x12, Bit 6) is set, it indicates that the synchronization logic has reached alignment. This alignment is determined when the clock generation state machine phase is constant. It takes between (11 + averaging) × 64 and (11 + averaging) × 128 DACCLK cycles. This bit may optionally ...
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... INTERRUPT REQUEST OPERATION The AD9122 provides an interrupt request output signal (on Pin 7, IRQ ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device ...
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... AD9122 INTERFACE TIMING VALIDATION The AD9122 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored ...
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... EXAMPLE START-UP ROUTINE There are certain sequences that should be followed to ensure reliable start-up of the AD9122. This section shows an example start-up routine assuming the configuration detailed in the following section. Device Configuration The following device configuration is used for this example 122.88MSPS DATA Interpolation = 4x, using HB1=’10’ and HB2=’ ...
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... PLANE ORDERING GUIDE 1 Model Temperature Range AD9122BCPZ −40°C to +85°C AD9122BCPZRL −40°C to +85°C AD9122-M5372-EBZ AD9122-M5375-EBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 0.42 0.24 ...