AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet - Page 51

• Manufacturer Part Number: AD9122-M5372-EBZ
• Description: DAC Evaluation Board W/ ADL5372 Modulator
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9122-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9122
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9122, ADL5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE POWER DISSIPATION
The AD9122 has four supply rails: AVDD33, IOVDD, DVDD18,
and CVDD18.
The AVDD33 supply powers the DAC core circuitry. The power
dissipation of the AVDD33 supply rail is independent of the digital
operating mode and sample rate. The current drawn from the
AVDD33 supply rail is typically 57 mA (188 mW) when the
full-scale current of the I and Q DACs is set to the nominal value
of 20 mA. Changing the full-scale current directly impacts the
supply current drawn from the AVDD33 rail. For example, if
the full-scale current of the I DAC and the Q DAC is changed to
10 mA, the AVDD33 supply current drops by 20 mA to 37 mA.
The IOVDD voltage supplies the serial port I/O pins, the RESET
pin, and the IRQ pin. The voltage applied to the IOVDD pin
can range from 1.8 V to 3.3 V. The current drawn by the
IOVDD supply pin is typically 3 mA.
The DVDD18 supply powers all of the digital signal processing
blocks of the device. The power consumption from this supply
is a function of which digital blocks are enabled and the frequency
at which the device is operating.
The CVDD18 supply powers the clock receiver and clock
distribution circuitry. The power consumption from this
supply varies directly with the operating frequency of the
device. CVDD18 also powers the PLL. The power dissipation
of the PLL is typically 80 mA when enabled.
Figure 77 through Figure 81 detail the power dissipation of the
AD9122 under a variety of operating conditions. All of the graphs
are taken with data being supplied to both the I and Q channels.
The power consumption of the device does not vary significantly
with changes in the coarse modulation mode selected or analog
output frequency. Graphs of the total power dissipation are shown
along with the power dissipation of the DVDD18 and CVDD18
supplies.
Maximum power dissipation can be estimated to be 20% higher
than the typical power dissipation.
Rev. A | Page 51 of 60
Figure 77. Total Power Dissipation vs. f
Figure 78. DVDD18 Power Dissipation vs. f
1700
1500
1300
1100
1200
1000
Figure 79. CVDD18 Power Dissipation vs. f
900
700
500
300
100
800
600
400
200
250
200
150
100
50
0
0
0
0
0
1×
2×
4×
8×
1×
2×
4×
8×
1×
2×
4×
8×
50
50
50
100
100
100
Inverse Sinc
Inverse Sinc
f
f
f
DATA
DATA
DATA
150
150
150
(MHz)
(MHz)
(MHz)
DATA
Without PLL, Fine NCO, and
DATA
200
200
200
DATA
Without Fine NCO and
with PLL Disabled
250
250
250
AD9122
300
300
300