AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet - Page 18

• Manufacturer Part Number: AD9122-M5372-EBZ
• Description: DAC Evaluation Board W/ ADL5372 Modulator
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9122-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9122
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9122, ADL5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIFFERENCES BETWEEN THE AD9122R1
AND AD9122R2
The AD9122 underwent a die revision in early 2010, that
incremented the die revision from R1 to R2. The following list
explains the differences between the revisions.
•
•
•
•
•
IOVDD supply voltage range.
For the AD9122R1, the valid operational range for IOVDD
is 1.8 V to 2.5 V ± 10%. For the AD9122R2, the valid
operational voltage range is 1.8 V to 3.3 V ± 10%.
Reduction in spurs level variation.
The AD9122R1 has a variation of the f
between device startups. The AD9122R2 has a consistent
and lower f
a spur level variation between power cycles of about 5 dB
if PLL is enabled.)
DCI delay feature added.
The AD9122R2 has a programmable delay associated with
the DCI signal. There are four programmable delay
options. The 00 setting gives minimum delay and leaves
the timing unchanged from the AD9122R1. Additional
delay can be added which may improve timing margins in
some systems. The resulting timing options are shown in
Table 14.
Power-down mode power consumption increase.
The maximum power-down mode power consumption
of the R1 devices is 9.8 mW. This power consumption
increased to 18.8 mW in the R2 devices.
Configuration register map changes.
Register 0x0B, Bit 5:
AD9122R1 Enable VCO
DATA
± f
OUT
spur level. (The AD9122R2 still has
DATA
± f
OUT
spur
Rev. A | Page 18 of 60
Device Marking of AD9122 R1 and AD9122 R2
Revision 1 devices are marked as shown in Figure 36. All
Revision 1 devices have date codes of earlier than #1021.
Revision 2 devices are marked as shown in Figure 37. All
Revision 2 devices have date codes of #1021 or later.
Register 0x16, Bits[1:0]:
Register 0x7F, Bits[5:2]:
AD9122R2 Inactive bit. The VCO is now enabled
when the PLL is enabled.
AD9122R1
AD9122R2
signal. 00 = minimum delay, 11 = maximum delay.
AD9122R1
AD9122R2
DATE CODE
Figure 37. Revision 2 Silicon, AD9122BCPZ Marking
Figure 36. AD9122, Revision 1 Marking
DATE CODE
Unused
These bits control the delay of the DCI
Version ID = 0x1
Version ID = 0x2
TxDAC
AD9122BCPZ
#0935
1688587.1
KOREA
®
TxDAC
AD9122BCPZ
#1021
1688782.1
KOREA
®
AD80255
AD9122BCPZ
#1001
1688586.1
KOREA
AD9122