AD9122-M5372-EBZ Analog Devices Inc, AD9122-M5372-EBZ Datasheet - Page 55

• Manufacturer Part Number: AD9122-M5372-EBZ
• Description: DAC Evaluation Board W/ ADL5372 Modulator
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9122-M5372-EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: DAC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9122
• Number Of Adc's: 2
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9122, ADL5372
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This completes the synchronization procedure, and at this stage,
all devices should be synchronized.
To ensure that each of the DACs are updated with the correct
data on the same CLK edge, two timing relationships must be
met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must
meet the setup-and-hold times with respect to the rising edge of
DACCLK, and REFCLK must also meet the setup-and-hold time
with respect to the rising edge of DACCLK. When resetting the
FIFO, the FRAME signal must be held high the time required to
input two complete data input words. When these conditions are
met, the outputs of the DACs are updated within t
nanoseconds of each other. A timing diagram that illustrates the
timing requirements of the input signals is shown in Figure 85.
DACCLKP(1)/
DACCLKP(2)/
Figure 85 shows the synchronization signal timing with 2×
interpolation; therefore, f
shown to be equal to the data rate. The maximum frequency at
which the device can be resynchronized in data rate mode can
be expressed as
where N is any nonnegative integer.
Generally, for values of N equal to or greater than 3, select the
FIFO rate synchronization mode.
FIFO RATE MODE SYNCHRONIZATION
The Procedure for FIFO Rate Synchronization when Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in FIFO rate mode.
The procedure assumes that the REFCLK and DACCLK signals
are applied to all of the devices. The procedure must be carried
out on each individual device.
Procedure for FIFO Rate Synchronization when Directly
Sourcing the DAC Sampling Clock
Configure for FIFO rate, periodic synchronization by writing
0x80 to the sync control register (Register 0x10). Additional
synchronization options are available and are described in the
Additional Synchronization Features section.
REFCLKP(2)/
DACCLKN(1)
DACCLKN(2)
REFCLKN(2)
FRAMEP(2)/
FRAMEN(3)
DCIP(2)/
DCIN(2)
Figure 85. Data Rate Synchronization Signal Timing Requirements,
f
SYNC_I
t
SU_DCI
= f
DATA
t
SKEW
t
/2
H_DCI
N
DCI
2x Interpolation
= ½ × f
t
SU_SYNC
CLK
. The REFCLK input is
t
H_SYNC
SKEW
+ t
OUTDLY
Rev. A | Page 55 of 60
Poll the sync locked bit (Register 0x12, Bit[6]) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for the time
required to input to complete input words. Resetting the FIFO
ensures that the correct data is being read from the FIFO of
each of the devices simultaneously.
This completes the synchronization procedure, and at this stage,
all devices should be synchronized.
To ensure that each of the DACs are updated with the correct
data on the same CLK edge, two timing relationships must be
met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must
meet the setup-and-hold times with respect to the rising edge of
DACCLK, and REFCLK must also meet the setup-and-hold
time with respect to the rising edge of DACCLK. When resetting
the FIFO, the FRAME signal must be held high for at least three
data periods (that is, 1.5 cycles of DCI). When these conditions
are met, the outputs of the DACs are updated within t
nanoseconds of each other. A timing diagram that illustrates the
timing requirements of the input signals is shown in Figure 86.
Figure 86 shows the synchronization signal timing with 2×
interpolation; therefore, f
shown to be equal to the FIFO rate. More generally, the maximum
frequency at which the device can be resynchronized in FIFO
rate mode can be expressed as
where N is any nonnegative integer.
ADDITIONAL SYNCHRONIZATION FEATURES
The synchronization logic incorporates additional features that
provide means for querying the status of the synchronization,
improving the robustness of the synchronization, and a one shot
synchronization mode. These features are detailed in the Sync
Status Bits and Timing Optimization sections that follow.
DACCLKP(1)/
DACCLKP(2)/
REFCLKP(2)/
DACCLKN(1)
DACCLKN(2)
REFCLKN(2)
FRAMEP(2)/
FRAMEN(2)
DCIP(2)/
DCIN(2)
Figure 86. FIFO Rate Synchronization Signal Timing Requirements,
f
SYNC_I
= (f
t
DATA
SKEW
/8 × 2
t
SU_SYNC
N
)
2× Interpolation
DCI
t
= ½ × f
H_SYNC
CLK
. The REFCLK input is
SKEW
AD9122
+ t
OUTDLY