PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 81
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 81 of 320
- Download datasheet (6Mb)
6.3.3
This mode allows Table Writes to any type of word-
wide external memories.
This method makes a distinction between TBLWT
cycles to even or odd addresses.
During a TBLWT cycle to an even address, where
TBLPTR<0> = 0, the TABLAT data is transferred to a
holding latch and the external address data bus is tri-
stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 6-9:
AD<15:0>
A<19:16>
2001 Microchip Technology Inc.
Instruction
Execution
Memory
WRH
WRL
Cycle
ALE
BA0
OE
UB
LB
’1’
EXTERNAL TABLE WRITE IN 16-BIT
WORD WRITE MODE
Q1
Opcode Fetch
3AAAh
from 007554h
INST(PC-2)
TBLWT*+
Q2
0h
Q3 Q4
TBLWT EXTERNAL INTERFACE TIMING (16-BIT WORD WRITE MODE)
000Dh
MOVWF TABLAT
TBLWT*+ Cycle1 TBLWT*+ Cycle2
Q1
Opcode Fetch
from 007556h
3AABh
Q2
0h
Q3 Q4
6FF4h
Advance Information
Q1
CF33h
TBLWT 56h
to 199E66h
Q2
Ch
Q3 Q4
During a TBLWT cycle to an odd address, where
TBLPTR<0> = 1, the TABLAT data is presented on the
upper byte of the AD<15:0> bus. The contents of the
holding latch are presented on the lower byte of the
AD<15:0> bus. The WRH line is strobed for each
write cycle and the WRL line is unused. The BA0 line
indicates the LSb of TBLPTR, but it is unnecessary.
The UB and LB lines are active to select both bytes.
The obvious limitation to this method is that the TBLWT
must be done in pairs on a specific word boundary to
correctly write a word location.
Figure 6-9 shows the timing associated with this mode.
Q1
Opcode Fetch
from 007558h
3AACh
MOVWF
TBLWT*
Q2
0h
Q3 Q4
000Ch
PIC18C601/801
Q1
TBLWT* Cycle1
Opcode Fetch
from 00755Ah
MOVLW 55h
3AADh
Q2
0h
Q3 Q4
0E55h
Q1
TBLWT* Cycle2
CF33h
TBLWT 92h
to 199E67h
DS39541A-page 81
Q2
Ch
Q3 Q4
9256h
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