PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 164
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 164 of 320
- Download datasheet (6Mb)
PIC18C601/801
15.4.4.1
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ’0’. Serial data is
transmitted eight bits at a time. After each byte is trans-
mitted, an Acknowledge bit is received. START and
STOP conditions are output to indicate the beginning
and the end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ’1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ’1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received eight bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. START and STOP conditions indicate the begin-
ning and end of transmission.
The baud rate generator used for the SPI mode opera-
tion is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generator will automatically begin counting on a write to
the SSPBUF. Once the given operation is complete
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
FIGURE 15-11:
DS39541A-page 164
2
C bus will not be released.
I
2
C Master Mode Operation
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SCL
2
C operation. The
SSPM3:SSPM0
Advance Information
Reload
Control
CLKOUT
Reload
A typical transmit sequence would go as follows:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
15.4.5
In I
located in the lower 7 bits of the SSPADD register
(Figure 15-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (T
and Q4 clocks. In I
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 15-12).
BRG Down Counter
2
SSPADD<6:0>
The user generates a START condition by set-
ting the START enable (SEN) bit (SSPCON2
register).
SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
The user loads the SSPBUF with the address to
transmit.
Address is shifted out the SDA pin until all eight
bits are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user loads the SSPBUF with eight bits of
data.
Data is shifted out the SDA pin until all eight bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit (SSPCON2 register).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit PEN (SSPCON2 register).
Interrupt is generated once the STOP condition
is complete.
C Master mode, the reload value for the BRG is
BAUD RATE GENERATOR
2
C Master mode, the BRG is
F
2001 Microchip Technology Inc.
OSC
/4
CY
) on the Q2
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