PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 170
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PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 170 of 320
- Download datasheet (6Mb)
PIC18C601/801
15.4.10
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence enable bit, ACKEN (SSPCON2
register). When this bit is set, the SCL pin is pulled low
and the contents of the Acknowledge Data bit (ACKDT)
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (T
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for T
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 15-17).
15.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t occur).
FIGURE 15-17:
FIGURE 15-18:
DS39541A-page 170
Note:
ACKNOWLEDGE SEQUENCE
TIMING
Note: T
T
BRG
BRG
SCL
SDA
SSPIF
= one baud rate generator period.
Acknowledge sequence starts here,
SDA
BRG
. The SCL pin is then pulled low. Fol-
SCL
Falling edge of
9th clock
Write to SSPCON2
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
= one baud rate generator period.
Set SSPIF at the end
of receive
ACK
ACKEN = 1, ACKDT = 0
Set PEN
Write to SSPCON2
BRG
8
T
T
D0
BRG
Advance Information
BRG
SDA asserted low before rising edge of clock
to set up STOP condition
) and the
T
SCL brought high after T
BRG
Cleared in
software
T
BRG
P
SCL = 1 for T
after SDA sampled high, P bit (SSPSTAT) is set
ACK
T
15.4.11
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT register) is set.
A T
is set (Figure 15-18).
15.4.11.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the contents
of the buffer are unchanged (the write doesn’t occur).
BRG
BRG
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
PEN bit (SSPCON2) is cleared by
later, the PEN bit is cleared and the SSPIF bit
hardware and the SSPIF bit is set
BRG
BRG
STOP CONDITION TIMING
, followed by SDA = 1 for T
WCOL Status Flag
ACKEN automatically cleared
Cleared in
software
2001 Microchip Technology Inc.
BRG
BRG
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