PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 80
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 80 of 320
- Download datasheet (6Mb)
PIC18C601/801
6.3.2
This mode allows Table Writes to byte-wide external
memories. During a TBLWT cycle, the TABLAT data is
presented on the upper and lower byte of the
AD<15:0> bus. The appropriate WRH or WRL line is
strobed based on the LSb of the TBLPTR. Figure 6-8
shows the timing associated with this mode.
FIGURE 6-8:
DS39541A-page 80
AD<15:0>
A<19:16>
Instruction
Execution
Memory
WRH
WRL
Cycle
ALE
BA0
OE
UB
LB
16-BIT EXTERNAL TABLE WRITE
(BYTE WRITE MODE)
Q1
Opcode Fetch
3AAAh
from 007554h
INST(PC-2)
TBLWT*+
Q2
0h
Q3 Q4
TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE WRITE MODE)
000Dh
MOVWF TABLAT
Q1
TBLWT*+ Cycle1
Opcode Fetch
from 007556h
3AABh
Q2
0h
Q3 Q4
6FF4h
Advance Information
Q1
TBLWT*+ Cycle2
CF33h
TBLWT 56h
to 199E66h
Q2
Ch
Q3 Q4
5656h
Q1
Opcode Fetch
from 007558h
3AACh
MOVWF
TBLWT*
Q2
0h
Q3 Q4
000Ch
Q1
Opcode Fetch
TBLWT* Cycle1
from 00755Ah
3AADh
MOVLW 55h
Q2
0h
Q3 Q4
2001 Microchip Technology Inc.
0E55h
Q1
TBLWT* Cycle2
CF33h
TBLWT 92h
to 199E67h
Q2
Ch
Q3 Q4
9292h
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