UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 406
![8BIT MCU, 4K FLASH, 256B RAM, 78F9222](/photos/19/3/190342/42268256_sml.jpg)
UPD78F9222MC(T)-5A4-A
Manufacturer Part Number
UPD78F9222MC(T)-5A4-A
Description
8BIT MCU, 4K FLASH, 256B RAM, 78F9222
Manufacturer
NEC
Datasheet
1.UPD78F9222MCT-5A4-A.pdf
(414 pages)
Specifications of UPD78F9222MC(T)-5A4-A
Controller Family/series
UPD78
No. Of I/o's
17
Ram Memory Size
256Byte
Cpu Speed
10MHz
No. Of Timers
4
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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Part Number:
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Quantity:
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Part Number:
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Edition
Modification of output width of INTTM010 and INTTM000 in the following figures
• Figure 6-17 CR010 Capture Operation with Rising Edge Specified
• Figure 6-20 Timing of Pulse Width Measurement Operation by Free-Running
• Figure 6-22 Timing of Pulse Width Measurement Operation with Free-Running
• Figure 6-24 Timing of Pulse Width Measurement Operation by Free-Running
• Figure 6-26 Timing of Pulse Width Measurement Operation by Means of Restart
Modification of Caution 1 in Figure 6-29 Control Register Settings for PPG Output
Operation
Modification of Figure 6-33 Timing of One-Shot Pulse Output Operation with
Software Trigger
Modification and addition to 6.5 Cautions Related to 16-bit Timer/Event Counter 00
Addition of Caution 2 to Figure 7-4 Format of 8-bit Timer Mode Control Register 80
(TMC80)
Modification of Table 9-1 Loop Detection Time of Watchdog Timer
Addition of Caution 4 and modification to Figure 9-2 Format of Watchdog Timer Mode
Register (WDTM)
Modification of Figure 9-4 Status Transition Diagram When “Low-Speed Internal
Oscillator Cannot Be Stopped” Is Selected by Option Byte
Modification of Figure 9-5 Status Transition Diagram When “Low-Speed Internal
Oscillator Can Be Stopped by Software” Is Selected by Option Byte
Addition of Note to and modification of Figure 10-1 Timing of A/D Converter Sampling
and A/D Conversion
Addition of Note 1, Caution, and Remark 2 to and modification of Table 10-1 Sampling
Time and A/D Conversion Time
Modification of Figure 10-2 Block Diagram of A/D Converter
Modification of Note 5, addition of Notes 1, 2, Cautions 1, 2, 4 and Remark 2 to, and
modification of Figure 10-3 Format of A/D Converter Mode Register (ADM)
Modification of Note in Figure 10-4 Timing Chart When Comparator Is Used
Addition of explanation <3> to 10.4.1 Basic operations of A/D converter
Modification of Figure 10-11 Relationship Between Analog Input Voltage and A/D
Conversion Result
Addition of explanation <3> to 10.4.3 A/D converter operation mode
Partial modification of 10.6 (1) Operating current in STOP mode and (6) Input
impedance of ANI0 to ANI3 pins
Modification of capacitor value in Figure 10-19 Analog Input Pin Connection
Modification of Figure 10-21 Internal Equivalent Circuit of ANIn Pin and Table 10-4
Resistance and Capacitance Values (Reference Values) of Equivalent Circuit
Addition of description to 11.2 (3) Transmit buffer register 6 (TXB6)
Modification of Note 1 in Figure 11-5 Format of Asynchronous Serial Interface
Operation Mode Register 6 (ASIM6) (1/2)
Modification of Caution in 11.3 (6) Asynchronous serial interface control register 6
(ASICL6)
Modification of Caution 1 in 11.4.2 (2) (d) Continuous transmission
Counter and One Capture Register (with Both Edges Specified)
Counter (with Both Edges Specified)
Counter and Two Capture Registers (with Rising Edge Specified)
(with Rising Edge Specified)
APPENDIX E REVISION HISTORY
User’s Manual U16898EJ5V0UD
Description
CHAPTER 6 16-BIT
TIMER/EVENT
COUNTER 00
CHAPTER 7 8-BIT
TIMER 80
CHAPTER 9
WATCHDOG TIMER
CHAPTER 10 A/D
CONVERTER
CHAPTER 11 SERIAL
INTERFACE UART6
Applied to:
(2/9)
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