UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 397

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

Standby
function
Reset
function
Power-on-
clear circuit
Function
OSTS:
Oscillation
stabilization
time select
register
HALT mode
setting and
operating
statuses
STOP mode
setting and
operating
statuses
Timing of reset
by overflow of
watchdog timer
RESF: Reset
control flag
register
Functions of
power-on-clear
circuit
Cautions for
power-on-clear
circuit
Details of
Function
−
Use these products in the following voltage range because the detection voltage
(V
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER
17 OPTION BYTE.
Because an interrupt request signal is used to clear the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask
flag clear, the standby mode is immediately cleared if set.
Because an interrupt request signal is used to clear the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set. Thus, in the STOP
mode, the normal operation mode is restored after the STOP instruction is
executed and then the operation is stopped for 34
wait time for stabilizing the oscillation set by the oscillation stabilization time
select register (OSTS) has elapsed when crystal/ceramic oscillation is used).
For an external reset, input a low level for 2
During reset signal generation, the system clock and low-speed internal
oscillation clock stop oscillating.
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KA1+
is reset if a low level is input to the RESET pin after reset is released by the
POC circuit, the LVI circuit and the watchdog timer and before the option byte is
referenced again. The reset status is retained until a high level is input to the
RESET pin.
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
The watchdog timer is also reset in the case of an internal reset of the watchdog
timer.
Do not read data by a 1-bit memory manipulation instruction.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to
5.5 V
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset
to the start of the operation of the microcontroller can be arbitrarily set by taking
the following action.
POC
) of the POC circuit is the supply voltage range.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ5V0UD
Cautions
POC
DD
) fluctuates for a certain period in the
), the system may be repeatedly reset
µ
s or more to the RESET pin.
µ
s (TYP.) (after an additional
p. 232
p. 232
p. 233
p. 236
p. 240
p. 240
p. 240
p. 241
p. 243
p. 247
p. 248
p. 248
p. 250
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