UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 40
UPD78F9222MC(T)-5A4-A
Manufacturer Part Number
UPD78F9222MC(T)-5A4-A
Description
8BIT MCU, 4K FLASH, 256B RAM, 78F9222
Manufacturer
NEC
Datasheet
1.UPD78F9222MCT-5A4-A.pdf
(414 pages)
Specifications of UPD78F9222MC(T)-5A4-A
Controller Family/series
UPD78
No. Of I/o's
17
Ram Memory Size
256Byte
Cpu Speed
10MHz
No. Of Timers
4
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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3.3 Instruction Address Addressing
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed.
information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S
Series Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
40
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
[Function]
[Illustration]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start
address of the following instruction is transferred to the program counter (PC) to branch. The displacement
value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words,
the range of branch in relative addressing is between –128 and +127 of the start address of the following
instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
PC
15
15
15
When S = 0,
When S = 1,
indicates that all bits are “0”.
indicates that all bits are “1”.
When a branch instruction is executed, the branch destination address
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U16898EJ5V0UD
8
PC
+
7
S
6
jdisp8
0
0
0
... PC is the start address of
the next instruction of
a BR instruction.
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