JN5148-001 Jennic LTD, JN5148-001 Datasheet - Page 48

• Manufacturer Part Number: JN5148-001
• Description: 32BIT, MCU, ZIGBEE PRO, 128K RAM, 56QFN
• Manufacturer: Jennic LTD

Specifications of JN5148-001

• No. Of I/o's: 21
• Eeprom Memory Size: 128KB
• Ram Memory Size: 128KB
• Cpu Speed: 32MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 3
• Digital Ic Case Style: QFN
• Core Size: 32bit
• Oscillator Type: External
• Peripherals: ADC, DAC, PWM, Timer
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Jennic
15.4 Slave Two-wire Serial Interface
When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal
low if it is required to apply clock stretching.
Only transfers whose address matches the value programmed into the interface’s address register are accepted. The
interface allows both 7 and 10 bit addresses to be programmed, but only responds with an acknowledge to a single
address. Addresses defined as “reserved” will not be responded to, and should not be programmed into the address
register. A list of reserved addresses is shown in Table 5.
Address
0000 000
0000 001
0000 010
0000 011
0000 1XX
1111 1XX
1111 0XX
Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for taking
write data from a receive buffer and providing read data to a transmit buffer when indicated. A series of interrupt
status bits are provided to control the flow of data.
For writes, in to the slave interface, it is important that data is taken from the receive buffer by the processor before
the next byte of data arrives. To enable this, the interface may be configured to work in two possible backoff modes:
For reads, from the slave interface, the data may be preloaded into the transmit buffer when it is empty (i.e. at the
start of day, or when the last data has been read), or fetched each time a read transfer is requested. When using data
preload, read data in the buffer must be replenished following a data write, as the transmit and received data is
contained in a shared buffer. The interface will hold the bus using clock stretching when the transmit buffer is empty.
Interrupts may be triggered when:
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Not Acknowledge mode – where the interface returns a Not Acknowledge (NACK) to the master if more data
is received before the previous data has been taken. This will lead to the termination of the current data
transfer.
Clock Stretching mode – where the interface holds the clock line low until the previous data has been taken.
This will occur after transfer of the next data but before issuing an acknowledge
Data Buffer read data is required – a byte of data to be read should be provided to avoid the interface from
clock stretching
Data Buffer read data has been taken – this indicates when the next data may be preloaded into the data
buffer
Data Buffer write data is available – a byte of data should be taken from the data buffer to avoid data backoff
as defined above
The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop or Restart is seen
A protocol error has been spotted on the interface
Table 5 : List of two-wire serial interface reserved addresses
Name
General Call/Start Byte
CBUS address
Reserved
Reserved
Hs-mode master code
Reserved
10-bit address
JN-DS-JN5148-001 1v2
Preliminary
Behaviour
Ignored
Ignored
Ignored
Ignored
Ignored
Ignored
Only responded to if 10 bit address
set in address register
© Jennic 2009