JN5148-001 Jennic LTD, JN5148-001 Datasheet - Page 33

• Manufacturer Part Number: JN5148-001
• Description: 32BIT, MCU, ZIGBEE PRO, 128K RAM, 56QFN
• Manufacturer: Jennic LTD

Specifications of JN5148-001

• No. Of I/o's: 21
• Eeprom Memory Size: 128KB
• Ram Memory Size: 128KB
• Cpu Speed: 32MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 3
• Digital Ic Case Style: QFN
• Core Size: 32bit
• Oscillator Type: External
• Peripherals: ADC, DAC, PWM, Timer
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5148 and
peripheral devices. The JN5148 operates as a master on the SPI bus and all other devices connected to the SPI are
expected to be slave devices under the control of the JN5148 CPU. The SPI includes the following features:
The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices
in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously.
There are three dedicated pins SPICLK, SPIMOSI, SPIMISO that are shared across all devices on the bus. Master-
Out-Slave-In or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN5148.
The JN5148 provides five slave selects, SPISEL0 to SPISEL4 to allow five SPI peripherals on the bus. SPISEL0 is a
dedicated pin; this is generally connected to a serial Flash/ EEPROM memory holding application code that is
downloaded to internal RAM via software from reset. SPISEL1 to 4, are alternate functions of pins DIO0 to 3
respectively.
The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted
between transfers when required, to enable longer transfers to be performed.
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16 MHz
Full-duplex, three-wire synchronous data transfer
Programmable bit rates (up to 16Mbit/s)
Programmable transaction size up to 32-bits
Standard SPI modes 0,1,2 and 3
Manual or Automatic slave select generation (up to 5 slaves)
Maskable transaction complete interrupt
LSB First or MSB First Data Transfer
Supports delayed read edges
Divider
Clock
Figure 19: SPI Block Diagram
JN-DS-JN5148-001 1v2
Preliminary
Data Buffer
Controller
SPI Bus
Cycle
Select
Latch
SPISEL [4..0]
SPIMISO
SPIMOSI
SPICLK
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