H27UF081G1M-TPCB HYNIX SEMICONDUCTOR, H27UF081G1M-TPCB Datasheet - Page 7

• Manufacturer Part Number: H27UF081G1M-TPCB
• Description: IC, MEMORY, FLASH NAND 1GB, TSOP48
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27UF081G1M-TPCB

• Access Time: 45ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Base Number: 27
• Interface: Serial
• Logic: RoHS Compliant
• Package / Case: TSOP
• Memory Type: Flash - NAND
• Memory Configuration: 128M X 8
• Rohs Compliant: Yes
• Memory Size: 1Gbit

1.2 PIN DESCRIPTION
Rev 0.2 / May. 2007
IO8-IO15(1)
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
Pin Name
IO0-IO7
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
VCC
CLE
ALE
VSS
R/B
WE
WP
NC
CE
RE
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE low does not deselect the
memory.
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
GROUND
NO CONNECTION
Table 2: Pin Description
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Description
HY27US(08/16)1G1M Series
Preliminary
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