ADXL180WCPZ-RL Analog Devices Inc, ADXL180WCPZ-RL Datasheet - Page 43

• Manufacturer Part Number: ADXL180WCPZ-RL
• Description: IC ACCELEROMETER CONFIG 16-LFCSP
• Manufacturer: Analog Devices Inc
• Series: iMEMS®r

Specifications of ADXL180WCPZ-RL

• Axis: X or Y
• Acceleration Range: ±50g, 100g, 150g, 200g, 250g, 350g, 500g
• Voltage - Supply: 5 V ~ 14.5 V
• Output Type: Analog
• Bandwidth: 100Hz ~ 800Hz Selectable
• Mounting Type: Surface Mount
• Package / Case: 16-LFQFN, CSP Exposed Pad
• Package Type: LFCSP EP
• Operating Supply Voltage (min): 5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Product Depth (mm): 5mm
• Product Height (mm): 1.43mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Interface: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ADXL180WCPZ-RLCT

ERROR DETECTION
OVERVIEW
The ADXL180 monitors its internal operation and reports
errors. The error reporting codes differ depending on whether
the state vector has been enabled. Table 39 describes the errors
and the specific codes transmitted in various configurations.
The state vector allows the ADXL180 to report specific errors if
enabled. If the state vector is not enabled, a single error code is
sent regardless of the type of error. The error code is transmitted
every 228 μs in asynchronous mode until power down. The
error code is transmitted in response to every synchronization
pulse in synchronous mode until power down.
Table 39. Status/Error Coding
Error
Configuration Error
Offset Error
Self-Test Error
OTP Parity Error
Device OK
Device Not OK (NOK)
1
A self-test error reported during Phase 5 indicates a failure of the internal self-test circuit, not a sensor self-test error.
0x7F
0x7E
0x7D
0x7C
0x7B
0x7A
Data Mode
8-Bit
State Vector Enabled
127d
126d
125d
124d
123d
122d
0x1F9
0x1F8
0x1F7
0x1F6
0x1E7
0x1F4
Data Mode
10-Bit
505d
504d
503d
502d
487d
500d
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0x7D
0x7D
0x7D
0x7D
0x7B
0x7D
Data Mode
8-Bit
State Vector Disabled
125d
125d
125d
125d
123d
125d
PARITY ERROR DUE TO COMMUNICATIONS
PROTOCOL CONFIGURATION BIT ERROR
As shown in Table 39, an error code is generated if the parity of
the ADXL180 device OTP memory is incorrect. However, if this
error is due to a parity error in one of the ERC, SVD, DAT, or MAN
bits that govern the format of the transmitted message, the error
code is transmitted in an alternate data format. Receive system
designs that recognize repeated message transmissions, wrong
data lengths, and incorrect Manchester encoding help to detect
more easily that an error code is being set.
0x1F4
0x1F4
0x1F4
0x1F4
0x1E7
0x1F4
Data Mode
10-Bit
500d
500d
500d
500d
487d
500d
Error Reporting Active in Phases
2
5
4, 5
4, 5
3
3, 4, 5
1
ADXL180