ADXL180WCPZ-RL Analog Devices Inc, ADXL180WCPZ-RL Datasheet - Page 30

• Manufacturer Part Number: ADXL180WCPZ-RL
• Description: IC ACCELEROMETER CONFIG 16-LFCSP
• Manufacturer: Analog Devices Inc
• Series: iMEMS®r

Specifications of ADXL180WCPZ-RL

• Axis: X or Y
• Acceleration Range: ±50g, 100g, 150g, 200g, 250g, 350g, 500g
• Voltage - Supply: 5 V ~ 14.5 V
• Output Type: Analog
• Bandwidth: 100Hz ~ 800Hz Selectable
• Mounting Type: Surface Mount
• Package / Case: 16-LFQFN, CSP Exposed Pad
• Package Type: LFCSP EP
• Operating Supply Voltage (min): 5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Product Depth (mm): 5mm
• Product Height (mm): 1.43mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Interface: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ADXL180WCPZ-RLCT

ADXL180
PHASE 2: MODE DESCRIPTION
Mode 0
The Mode 0 option for Phase 2 transmits the entire contents of
the configuration registers, the serial number and the manufac-
turer ID byte. The total number of messages transmitted during
Phase 2, Mode 0 is 9.
Table 26. Mode 0 Serial Number and Configuration Data Byte Sequence
Byte 8
CREG2
Table 27. Mode 0 Manufacturer ID Byte
MSB
SNPRG
Byte 7
CREG1
SNPAR
Byte 6
CREG0
REV2
9 ×
t
P
Byte 5
UREG
REV1
Figure 23. Phase 2 Mode 0 State Machine
Byte 4
Manufacturer ID
REV0
TRANSMIT MANUFACTURER ID
Rev. A | Page 30 of 60
TRANSMIT CREG0 BYTE
TRANSMIT CREG1 BYTE
TRANSMIT CREG2 BYTE
TRANSMIT UREG BYTE
TRANSMIT SN0 BYTE
TRANSMIT SN1 BYTE
TRANSMIT SN2 BYTE
TRANSMIT SN3 BYTE
PHASE 1
PHASE 3
BYTE
Asynchronous Mode
The device data is transmitted at a time interval of 456 μs based
on the internal clock of the ADXL180. The 456 μs period is
twice the normal transmission time interval of 228 μs.
Synchronous Mode
In synchronous mode, the device data is transmitted in
response to the synchronization pulse generated by the control
module. See the Synchronization Pulse Detection section.
MFGID2
t
t
t
t
t
t
t
t
t
P
P
P
P
P
P
P
P
P
Byte 3
SN3
PHASE 2
MODE 0
MFGID1
Byte 2
SN2
Byte 1
SN1
LSB
MFGID0
Byte 0
SN0