NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 434
![KIT EVAUATION NUC100/120/130/140](/photos/18/31/183177/numicro-sdk_sml.jpg)
NUMICRO-SDK
Manufacturer Part Number
NUMICRO-SDK
Description
KIT EVAUATION NUC100/120/130/140
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Type
MCUr
Datasheets
1.NUC100LC1BN.pdf
(600 pages)
2.NUMICRO-SDK.pdf
(13 pages)
3.NUMICRO-SDK.pdf
(93 pages)
4.NUMICRO-SDK.pdf
(1 pages)
Specifications of NUMICRO-SDK
Contents
Board, Cable, CD, Nu-Link
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
NUC100, NUC120, NUC130, NUC140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
Nuvoton Technology Corporation
Quantity:
135
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
NuvoTon
Quantity:
69
- NUC100LC1BN PDF datasheet
- NUMICRO-SDK PDF datasheet #2
- NUMICRO-SDK PDF datasheet #3
- NUMICRO-SDK PDF datasheet #4
- Current page: 434 of 600
- Download datasheet (6Mb)
Interrupt Status Register (INTR)
Register
INTR
Bits
[31:8]
[7]
[6]
[5]
[4]
[3:2]
[1]
[0]
BEI
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
CAN0_BA+0x0C
Descriptions
Reserved
BEI
ALI
Reserved
WUI
Reserved
TI
RI
ALI
30
22
14
6
Reserved
R/W
R/W
Reserved
Bus Error Interrupt
1 = This bit will be set when this CAN node detects an error on the CAN-bus and the
0 = No bus error interrupt
Arbitration Lost Interrupt
1 = This bit will be set when this CAN node lose the arbitration to become a receiver
0 = No arbitration lost interrupt
Reserved
Wake-Up Interrupt
1 = This bit will be set when this CAN node is sleeping but be waked up by bus activity
If the wakeup interrupt active after power idle, the WAKEUP_EN bit shall be clear
before this bit to be cleared.
0 = No wake-up interrupt
Reserved
Transmit Interrupt
1 = This bit will be set when a transmission has done and the TIE bit is set within the
0 = No transmit done information
Receive Interrupt
1 = This bit will be set when a frame receiving has done and the RIE bit is set within
29
21
13
5
BEIE bit is set within the interrupt enable register. It will be clear by write 1 to this
bit.
and the ALIE bit is set within the interrupt enable register. It will be clear by write 1
to this bit.
and the WUIE bit is set within the interrupt enable register. It will be clear by write 1
to this bit.
interrupt enable register. It will be clear by write 1 to this bit.
the interrupt register. It will be clear by write 1 to this bit.
Description
Interrupt Status Register
WUI
28
20
12
4
- 434 -
Reserved
Reserved
Reserved
27
19
11
3
Reserved
Publication Release Date: Dec. 22, 2010
26
18
10
2
25
17
TI
9
1
Revision V1.06
Reset Value
0x0000_0000
24
16
RI
8
0
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