NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 315
![KIT EVAUATION NUC100/120/130/140](/photos/18/31/183177/numicro-sdk_sml.jpg)
NUMICRO-SDK
Manufacturer Part Number
NUMICRO-SDK
Description
KIT EVAUATION NUC100/120/130/140
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Type
MCUr
Datasheets
1.NUC100LC1BN.pdf
(600 pages)
2.NUMICRO-SDK.pdf
(13 pages)
3.NUMICRO-SDK.pdf
(93 pages)
4.NUMICRO-SDK.pdf
(1 pages)
Specifications of NUMICRO-SDK
Contents
Board, Cable, CD, Nu-Link
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
NUC100, NUC120, NUC130, NUC140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
Nuvoton Technology Corporation
Quantity:
135
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
NuvoTon
Quantity:
69
- NUC100LC1BN PDF datasheet
- NUMICRO-SDK PDF datasheet #2
- NUMICRO-SDK PDF datasheet #3
- NUMICRO-SDK PDF datasheet #4
- Current page: 315 of 600
- Download datasheet (6Mb)
Capture Control Register (CCR2)
Register
CCR2
Bits
[31:24]
[23]
[22]
[21]
[20]
[19]
CFLRI3
CFLRI2
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
PWMA_BA+0x54 R/W
PWMB_BA+0x54 R/W
Descriptions
Reserved
CFLRI3
CRLRI3
Reserved
CAPIF3
CAPCH3EN
CRLRI3
CRLRI2
30
22
14
6
Reserved
Reserved
R/W
Reserved
CFLR3 Latched Indicator Bit
When PWM group input channel 3 has a falling transition, CFLR3 was latched with the
value of PWM down-counter and this bit is set by hardware.
In Medium Density, software can write 0 to clear this bit to zero.
In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can
Write 1 to clear this bit to zero if BCn bit is 1.
CRLR3 Latched Indicator Bit
When PWM group input channel 3 has a rising transition, CRLR3 was latched with the
value of PWM down-counter and this bit is set by hardware.
In Medium Density, software can write 0 to clear this bit to zero.
In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can
Write 1 to clear this bit to zero if BCn bit is 1.
Reserved
Channel 3 Capture Interrupt Indication Flag
If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising
transition occurs at PWM group channel 3 will result in CAPIF3 to high; Similarly, a
falling transition will cause CAPIF3 to be set high if PWM group channel 3 falling latch
interrupt is enabled (CFL_IE3=1).
Write 1 to clear this bit to zero
Channel 3 Capture Function Enable
1 = Enable capture function on PWM group channel 3
0 = Disable capture function on PWM group channel 3
When Enable, Capture latched the PWM-counter and saved to CRLR (Rising latch)
29
21
13
5
Description
PWM Group A Capture Control Register
PWM Group B Capture Control Register
(Medium Density Only)
CAPIF3
CAPIF2
28
20
12
4
- 315 -
Reserved
Reserved
CAPCH3EN
CAPCH2EN
27
19
11
3
Publication Release Date: Oct 22, 2010
FL_IE3
FL_IE2
26
18
10
2
RL_IE3
RL_IE2
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
0x0000_0000
INV3
INV2
24
16
8
0
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