NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 122
NUMICRO-SDK
Manufacturer Part Number
NUMICRO-SDK
Description
KIT EVAUATION NUC100/120/130/140
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Type
MCUr
Datasheets
1.NUC100LC1BN.pdf
(600 pages)
2.NUMICRO-SDK.pdf
(13 pages)
3.NUMICRO-SDK.pdf
(93 pages)
4.NUMICRO-SDK.pdf
(1 pages)
Specifications of NUMICRO-SDK
Contents
Board, Cable, CD, Nu-Link
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
NUC100, NUC120, NUC130, NUC140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
Nuvoton Technology Corporation
Quantity:
135
Company:
Part Number:
NUMICRO-SDK
Manufacturer:
NuvoTon
Quantity:
69
- NUC100LC1BN PDF datasheet
- NUMICRO-SDK PDF datasheet #2
- NUMICRO-SDK PDF datasheet #3
- NUMICRO-SDK PDF datasheet #4
- Current page: 122 of 600
- Download datasheet (6Mb)
Peripheral Reset Control Register1 (IPRSTC1)
Register
IPRSTC1
Bits
[31:4]
[3]
[2]
[1]
[0]
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
EBI_RST
PDMA_RST
CPU_RST
CHIP_RST
Offset
GCR_BA+0x08
30
22
14
6
Reserved
R/W
R/W
Reserved
EBI Controller Reset (Low Density 64 pin package Only) (write-protection bit in
NUC100/NUC120/NUC130/NUC140 Low Density 64-pin package)
Set this bit to 1 will generate a reset signal to the EBI. User need to set this bit to 0 to
release from the reset state.
This bit is the protected bit, It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100
1 = EBI controller reset
0 = EBI controller normal operation
PDMA Controller Reset (write-protection bit in NUC100/NUC120/NUC130/NUC140
Low Density)
Setting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to
0 to release from reset state.
This bit is the protected bit, It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100.
1 = PDMA controller reset
0 = PDMA controller normal operation
CPU kernel one shot reset (write-protection bit)
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and
this bit will automatically return to 0 after the 2 clock cycles
This bit is the protected bit, It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100
1 = CPU one shot reset
0 = CPU normal operation
CHIP one shot reset (write-protection bit)
29
21
13
5
Description
IP Reset Control Register 1
28
20
12
4
- 122 -
Reserved
Reserved
Reserved
EBI_RST
27
19
11
3
Publication Release Date: Dec. 22, 2010
PDMA_RST
26
18
10
2
CPU_RST
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
CHIP_RST
24
16
8
0
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