PCF85132U/2DA/1,02 NXP Semiconductors, PCF85132U/2DA/1,02 Datasheet - Page 7

• Manufacturer Part Number: PCF85132U/2DA/1,02
• Description: IC LCD DISPLAY DRVR UNCASED
• Manufacturer: NXP Semiconductors

Specifications of PCF85132U/2DA/1,02

• Display Type: LCD
• Configuration: Multiple
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 60µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCF85132
Product data sheet
7.1 Power-On Reset (POR)
7.2 LCD bias generator
The host microprocessor or microcontroller maintains the 2-line I
channel with the PCF85132.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to V
power supplies (V
At power-on the PCF85132 resets to the following starting conditions:
Remark: Do not transfer data on the I
the reset action to complete.
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three
series resistors connected between V
switch if the
Fig 4.
•
•
•
•
•
•
•
•
All backplane and segment outputs are set to V
The selected drive mode is 1:4 multiplex with
Blinking is switched off
Input and output bank selectors are reset
The I
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled
If internal oscillator is selected (pin OSC connected to V
signal on pin CLK
V
V
DD
SS
CONTROLLER
2
PROCESSOR/
Typical system configuration
C-bus interface is initialized
MICRO-
MICRO-
HOST
1
SS
⁄
2
bias voltage level for the 1:2 multiplex configuration is selected.
. The only other connections required to complete the system are the
All information provided in this document is subject to legal disclaimers.
R ≤
DD
2C
t
, V
r
B
Rev. 1 — 23 November 2010
SS
, and V
SDAACK
LCD
OSC
SDA
SCL
) and the LCD panel selected for the application.
LCD
2
C-bus for at least 1 ms after a power-on to allow
and V
A0
PCF85132
V
DD
A1 SA0
SS
V
1
. The center resistor is bypassed by
LCD
⁄
3
LCD
bias
V
LCD driver for low multiplex rates
SS
160 segment drives
4 backplanes
SS
), then there is no clock
2
C-bus communication
PCF85132
© NXP B.V. 2010. All rights reserved.
LCD PANEL
(up to 640
elements)
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