PCF85132U/2DA/1,02 NXP Semiconductors, PCF85132U/2DA/1,02 Datasheet - Page 16

• Manufacturer Part Number: PCF85132U/2DA/1,02
• Description: IC LCD DISPLAY DRVR UNCASED
• Manufacturer: NXP Semiconductors

Specifications of PCF85132U/2DA/1,02

• Display Type: LCD
• Configuration: Multiple
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 60µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCF85132
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing and frame frequency
7.7 Display register
The internal logic and the LCD drive signals of the PCF85132 are timed by a frequency f
which either is derived from the built-in oscillator frequency f
or equals an external clock frequency f
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
The internal oscillator is enabled by connecting pin OSC to V
from pin CLK provides the clock signal for cascaded PCF85132 in the system. However,
the clock signal is only available at pin CLK, if the display is enabled. The display is
enabled using the display enable bit (see
The output clock frequency is like specified in
Connecting pin OSC to V
external clock input.
The timing of the PCF85132 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF85132 in the system.
When the internal clock is used, the clock frequency can be programmed by software
such that the frame frequency can be chosen in steps of 5 Hz in the range of 60 Hz to
90 Hz (see
±10 % (at V
The timing also generates the LCD frame frequency derived from an integer division of f
(see
The display register holds the display data while the corresponding multiplex signals are
generated.
f
f
clk
clk
Table 16 on page
=
=
f
------- -
f
64
osc
clk ext
(
Table 16 on page
DD
)
= 5.0 V; T
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 November 2010
28).
amb
DD
enables an external clock source. Pin CLK then becomes the
= 30 °C).
28). The internal oscillator is calibrated within an accuracy of
clk(ext)
Table 10 on page
:
Table 19 on page 34
LCD driver for low multiplex rates
26).
osc
SS
:
. In this case the output
with parameter f
PCF85132
© NXP B.V. 2010. All rights reserved.
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clk
.
(6)
(7)
clk
clk