PCF85132U/2DA/1,02 NXP Semiconductors, PCF85132U/2DA/1,02 Datasheet - Page 34

• Manufacturer Part Number: PCF85132U/2DA/1,02
• Description: IC LCD DISPLAY DRVR UNCASED
• Manufacturer: NXP Semiconductors

Specifications of PCF85132U/2DA/1,02

• Display Type: LCD
• Configuration: Multiple
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 60µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
11. Dynamic characteristics
Table 19.
V
[1]
[2]
[3]
[4]
[5]
PCF85132
Product data sheet
Symbol
f
f
t
t
Δf
t
t
t
Timing characteristics: I
f
t
t
t
t
t
t
t
t
C
t
t
t
t
clk
clk(ext)
clk(H)
clk(L)
PD(SYNC_N)
SYNC_NL
PD(drv)
SCL
BUF
HD;STA
SU;STA
VD;ACK
LOW
HIGH
f
r
SU;DAT
HD;DAT
SU;STO
SP
DD
b
fr
= 1.8 V to 5.5 V; V
Typical output duty factor: 50 % measured at the CLK output pin.
For the respective frame frequency f
For the characteristics of V
For f
should be between 100 kΩ and 1 MΩ.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
input voltage swing of V
CLK(ext)
Dynamic characteristics
Parameter
clock frequency
external clock frequency
HIGH-level clock time
LOW-level clock time
frame frequency variation
SYNC propagation delay
SYNC LOW time
driver propagation delay
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START condition
data valid acknowledge time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time
rise time
capacitive load for each bus line
data set-up time
data hold time
set-up time for STOP condition
pulse width of spikes that must be
suppressed by the input filter
> 4 kHz it is recommended to use an external pull-up resistor between pin SYNC and pin V
SS
SS
= 0 V; V
2
C-bus
to V
DD
at a fixed temperature or of the temperature at a fixed V
DD
[5]
LCD
.
fr
= 1.8 V to 8.0 V; T
see
Table
All information provided in this document is subject to legal disclaimers.
16.
Rev. 1 — 23 November 2010
amb
on pin CLK;
external clock source used
V
V
of both SDA and SCL signals
of both SDA and SCL signals
Conditions
V
external clock source used
=
DD
DD
LCD
f
f
f
fr
fr
fr
−
40
= 5 V ± 0.5 V
= 5 V ± 0.5 V
= 80 Hz; T
= 75 Hz; T
= 71 Hz; T
= 5 V
°
C to +85
amb
amb
amb
°
C; unless otherwise specified.
= −40 °C
= 30 °C
= 85 °C
DD
, see
LCD driver for low multiplex rates
Figure 22
[1][2][3]
[4]
DD
and
Min
1600 1800 2060 Hz
700
100
100
−15
−10
−15
-
100
-
-
1.3
0.6
0.6
-
1.3
0.6
-
-
-
200
0
0.6
-
. The value of the resistor
PCF85132
Figure
© NXP B.V. 2010. All rights reserved.
Typ
-
-
-
-
-
-
30
-
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23.
IL
and V
Max
5000 Hz
-
-
+15
+10
+15
-
-
-
400
-
-
-
0.9
-
-
0.3
0.3
400
-
-
-
50
IH
34 of 54
with an
kHz
Unit
μs
μs
%
%
%
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns
μs
ns